Patent
Reduced-voltage NMOS output driver
TLDR
In this article, a tri-state output buffer circuit employs N-channel pull-up and pull-down transistors, with a P-channel and an Nchannel transistor responsive to the logic input.Abstract:
A tri-state output buffer circuit employs N-channel pull-up and pull-down transistors, with another N-channel transistor connected between the pull-up and pull-down transistors and having its gate connected to the low-voltage supply. An output node at one side of the pull-up transistor may be driven to a voltage higher than the supply, without subjecting the pull-up to hot-carrier effects or other deleterious effects of over-voltage. When in the high-impedance output state, the gate of the pull-up is shorted to an intermediate node which is the drain of the pull-down transistor, using a P-channel and an N-channel transistor responsive to the logic input. The voltage on the gate of the pull-up transistor is allowed to track the output up to the reduced voltage supply minus V TN when in the high-impedance state, by tying the gate of the pull-up transistor to the intermediate node; this prevents damage to the pull-up due to hot-carrier effects.read more
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Patent
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References
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Patent
Low-voltage CMOS output buffer
TL;DR: In this article, the P-channel pull-up transistor (11) of a push-pull output buffer was used to resist the voltage elevation of the output node to higher voltage without sinking large currents into the low-voltage supply.
Patent
Floating-well CMOS output driver
TL;DR: In this paper, a CMOS bi-directional output driver for a 3.3-volt bi-input-multiple-output (BIMO) system was presented.
Patent
CMOS off-chip driver circuit
TL;DR: In this paper, a CMOS off-chip driver circuit is provided which includes a first P-channel field effect transistor (32) arranged in series with a second or pull-up P-Channel transistor (30) and a third Pchannel transistor (36) connected from the common point (B) between the first and second transistors (32, 30) and the gate electrode of the first transistor(32), with its gate electrode being connected to the data output terminal.
Patent
MOS no-leak circuit
Donald G. Tipon,Chinh V. Tran +1 more
TL;DR: In this article, a CMOS inverter circuit is coupled to a power source by a cut-off circuit which prevents current flow through the inverter when the input signal to the CMOS input signal is of a first bi-level state.
Patent
Current limiting MOS transistor driver circuit
TL;DR: In this paper, a current limiting driver circuit (10) receives a first logic level input signal (φ 1 ) and drives an output pin (26) to ground by a pull-down transistor.