Tri-state nanoelectromechanical (NEM) memory switches are proposed for the implementation of high-impedance state 0 in addition to low-impedance states 1 and 2 for the improvement of conventional complementary metal-oxide-semiconductor-NEM (CMOS-NEM) reconfigurable logic (RL) operations. Although it is well known that the high impedance state of routing switches is essential to prevent the unnecessary data throughput of RL circuits, previously proposed NEM memory switches have only implemented binary states: states 1 and 2. On the contrary, our proposed NEM memory switches can have tri-states, which are achieved by modifying their operation methods and design guidelines.

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Selection Line Optimization of Nanoelectromechanical (NEM) Memory Switches for Stress Relief

Tri-State Nanoelectromechanical Memory Switches for the Implementation of a High-Impedance State

A tristate-nanoelectromechanical-switch-based ternary content-addressable memory (NEMTCAM) is proposed for the first time. In the proposed unit NEMTCAM cell, a single nanoelectromechanical (NEM) memory switch replaces two static random access memory cells. Due to the monolithic 3-D (M3D) integration and nonvolatile property of NEM memory switches, the proposed NEMTCAM achieves an 86.3% smaller area, 75.0% lower dynamic power consumption, and a 76.6% higher search speed than conventional ternary content-addressable memory (TCAM) in addition to a negligible static leakage current.

Selection Line Optimization of Nanoelectromechanical (NEM) Memory Switches for Stress Relief

Citations

Tri-State Nanoelectromechanical Memory Switches for the Implementation of a High-Impedance State

Nanoelectromechanical-Switch-Based Ternary Content-Addressable Memory (NEMTCAM)

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