Patent
Semiconductor memory capable of being driven at low voltage and its manufacture method
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TLDR
In this paper, a gate is formed in a partial area of the surface of a semiconductor substrate, and on this gate insulating film, a gate electrode is formed, conformable to the side wall and the surface.Abstract:
A gate insulating film is formed in a partial area of the surface of a semiconductor substrate, and on this gate insulating film, a gate electrode is formed. An ONO film is formed on the side wall of the gate electrode and on the surface of the semiconductor substrate on both sides of the gate electrode, conformable to the side wall and the surface. A silicon nitride film of the ONO film traps carriers. A conductive side wall spacer faces the side wall of the gate electrode and the surface of the semiconductor substrate via the ONO film. A conductive connection member electrically connects the side wall spacer and gate electrode. Source and drain regions are formed in the surface layer of the semiconductor substrate in areas sandwiching the gate electrode. A semiconductor device is provided which can store data of two bits in one memory cell and can be driven at a low voltage.read more
Citations
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Patent
Semiconductor integrated circuit device and a method of manufacturing the same
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Nonvolatile semiconductor memory device and manufacturing method thereof
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Eduardo Maayan,Boaz Eitan +1 more
TL;DR: A die for a memory array may store Flash and EEPROM bits in at least one Nitride Read Only Memory (NROM) array as mentioned in this paper, and each array can store Flash, EPROM or both types of bits.
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Method for programming a reference cell
TL;DR: In this paper, a method for programming one or more reference cells is described, where the reference cell is programmed a predetermined amount, its program state is sensed relative to a prescribed cell on the same die (e.g., a memory cell or a golden bit cell), and the programming process continues until the reference cells fails a preselected read operation.
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EEPROM array and method for operation thereof
TL;DR: In this paper, a method for operating an electrically erasable programmable read-only memory (EEPROM) array is described, where each memory cell is connected to a word line and to two bit lines, selecting one of the memory cells and erasing a bit of the selected memory cell while applying an inhibit word line voltage to a gate of an unselected memory cell.
References
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Journal ArticleDOI
NROM: A novel localized trapping, 2-bit nonvolatile memory cell
TL;DR: In this paper, a novel flash memory cell based on localized charge trapping in a dielectric layer and on a new read operation is presented, which is based on the storage of a nominal /spl sim/400 electrons above a n/sup +//p junction.
Patent
Process for making and programming and operating a dual-bit multi-level ballistic flash memory
Seiki Ogura,Tomoko Ogura +1 more
TL;DR: In this article, an ultra-high density, dual-bit, multi-level flash memory process is described, which can be applied to a ballistic step split gate side wall transistor, or a ballistic planar split gate SL transistor, which enables program operation by low voltage requirement on the floating gate during program.
Patent
Self-aligned, split-gate EEPROM device
TL;DR: In this paper, an EEPROM device capable of operating with a single lowvoltage power supply includes a control gate electrode (30) and a select gate electrode(14) overlying separate portions of a channel region (32).
Patent
Split-gate memory device and method for accessing the same
TL;DR: In this article, a split-gate FET (10) having a source (36), a drain (22), a select gate (16) adjacent the drain, and a control gate (32) adjacent to the source was used to accelerate a portion of a channel region between the select gate and the control gate.
Journal ArticleDOI
A new SONOS memory using source-side injection for programming
TL;DR: In this article, a new polysiliconoxide-nitride-oxide-silicon (SONOS) nonvolatile memory using channel hot electron injection for high-speed programming was presented.