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Sequential Optimization of Asynchronous and Synchronous Finite-State Machines: Algorithms and Tools
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TLDR
Minimalist: An Extensible Toolkit for Burst-Mode Synthesis and Optimist: Optimal State Minimization for Synchronous FSM's are presented.Abstract:
List of Figures. List of Tables. Acknowledgments. 1. Introduction. 2. Background. 3. Burst-Mode Synthesis Path Walk-Through. 4. CHASM: Optimal State Assignment for Asynchronous FSM's. 5. Optimist: Optimal State Minimization for Synchronous FSM's. 6. Optimisto-Synchronous State Minimization for Optimum Output Logic. 7. Optimista: Asynchronous State Minimization for Optimum Output Logic. 8. Minimalist: An Extensible Toolkit for Burst-Mode Synthesis. 9. Conclusions. Appendices. Index.read more
Citations
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Journal ArticleDOI
Robust interfaces for mixed-timing systems
Tiberiu Chelcea,Steven M. Nowick +1 more
TL;DR: This paper presents several low-latency mixed-timing FIFO (first-in-first-out) interfaces designs that interface systems on a chip working at different speeds and initial simulations for both latency and throughput are promising.
Journal ArticleDOI
Elastic Circuits
TL;DR: Synchronous and asynchronous elastic circuits can be designed, analyzed, and optimized using similar techniques, and choices between synchronous and asynchronous implementations are localized and deferred until late in the design process.
Patent
Low latency fifo circuits for mixed asynchronous and synchronous systems
Tiberiu Chelcea,Steven M. Nowick +1 more
TL;DR: In this paper, a mixed-clock relay station design interfaces a sender subsystem and a receiver subsystem working at different time domains, and where the latency between sender and receiver is large.
Journal ArticleDOI
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
TL;DR: A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS)chip multiprocessors that eliminates the need for global clock distribution, and can interface multiple synchronous timing domains operating at unrelated clock rates.
Proceedings ArticleDOI
Low-latency asynchronous FIFO's using token rings
Tiberiu Chelcea,Steven M. Nowick +1 more
TL;DR: This paper presents several new asynchronous FIFO designs implemented as circular arrays of cells connected to common data buses, with a goal to achieve very low latency while maintaining good throughput.