Journal ArticleDOI
Use of minimum-adder multiplier blocks in FIR digital filters
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TLDR
Three new algorithms for the design of multiplier blocks are described: an efficient modification to an existing algorithm, a new algorithm giving better results, and a hybrid of these two which trades off performance against computation time.Abstract:
The computational complexity of VLSI digital filters using fixed point binary multiplier coefficients is normally dominated by the number of adders used in the implementation of the multipliers. It has been shown that using multiplier blocks to exploit redundancy across the coefficients results in significant reductions in complexity over methods using canonic signed-digit (CSD) representation, which in turn are less complex than standard binary representation. Three new algorithms for the design of multiplier blocks are described: an efficient modification to an existing algorithm, a new algorithm giving better results, and a hybrid of these two which trades off performance against computation time. Significant savings in filter implementation cost over existing techniques result in all three cases. For a given wordlength, it was found that a threshold set size exists above which the multiplier block is extremely likely to be optimal. In this region, design computation time is substantially reduced. >read more
Citations
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Journal ArticleDOI
Multiplierless multiple constant multiplication
Yevgen Voronenko,Markus Püschel +1 more
TL;DR: This work proposes a new algorithm for the multiple constant multiplication problem, which produces solutions that require up to 20% less additions and subtractions than the best previously known algorithm and can handle problem sizes as large as 100 32-bit constants in a time acceptable for most applications.
Journal ArticleDOI
A new algorithm for elimination of common subexpressions
TL;DR: A new solution of the multiple constant multiplication problem based on the common subexpression elimination technique is presented and it is shown that the number of add/subtract operations can be reduced significantly this way.
Journal ArticleDOI
Design of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm
TL;DR: Main results show that the NR-SCSE implementations of several benchmark circuits offer the best relation between occupied area and logic depth respect to the previous values published in the technical literature.
Journal ArticleDOI
Algorithms for low power and high speed FIR filter realization using differential coefficients
TL;DR: In this article, a set of new algorithms for low power and high speed realization of FIR filters are presented, which use various orders of differences between coefficients for computing the convolution.
Journal ArticleDOI
A trellis search algorithm for the design of FIR filters with signed-powers-of-two coefficients
Chao-Liang Chen,A.N. Willson +1 more
TL;DR: In this paper, an efficient two-stage algorithm is presented for designing finite-impulse response (FIR) filters that employ sums of signed-powers-of-two (SPT) coefficients.
References
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Book
Computers and Intractability: A Guide to the Theory of NP-Completeness
TL;DR: The second edition of a quarterly column as discussed by the authors provides a continuing update to the list of problems (NP-complete and harder) presented by M. R. Garey and myself in our book "Computers and Intractability: A Guide to the Theory of NP-Completeness,” W. H. Freeman & Co., San Francisco, 1979.
Journal ArticleDOI
Signed-Digit Numbe Representations for Fast Parallel Arithmetic
TL;DR: Sign-digit representations limit carry-propagation to one position to the left during the operations of addition and subtraction in digital computers and arithmetic operations with signed-digit numbers: addition, subtraction, multiplication, division and roundoff are discussed.
Journal ArticleDOI
FIR filter design over a discrete powers-of-two coefficient space
TL;DR: In this article, a digital filter with discrete coefficient values selected from the powers-of-two coefficient space is designed using the methods of integer programming, and the frequency responses obtained are shown to be superior to those obtained by simply rounding the coefficients.