Solid-state delay line

TLDR: In this article, a field effect transistor with a gate electrode which is considerably extended in the direction of the semiconductor current channel is described, and a solid-state delay line is disclosed, where two DC voltage sources are connected to the source and drain electrodes and to the ends of the gate electrode.

Abstract: A solid-state delay line is disclosed which includes a field effect transistor with a gate electrode which is considerably extended in the direction of the semiconductor current channel. Two DC voltage sources are connected to the source and drain electrodes and to the ends of the gate electrode, respectively, and cause currents to be adjusted such that the voltage drops per unit length in the semiconductor channel and in the gate electrode are equal. A uniform thickness of the charge carrier variation zone, i.e., a depletion zone or an enhancement zone, is obtained in the semiconductor channel and the delay of signals propagating through the semiconductor channel is proportional to the length of the extended gate electrode.