Journal ArticleDOI
Subnanosecond emitter-coupled logic gate circuit using Isoplanar II
TLDR
Describes a 650-ps propagation delay voltage and temperature compensated emitter-coupled logic dual-gate circuit using a new and significantly improved transistor structure that is significant improvement in switching performance without any sacrifice in voltage levels and voltage supply tolerances.Abstract:
Describes a 650-ps propagation delay voltage and temperature compensated emitter-coupled logic dual-gate circuit using a new and significantly improved transistor structure. The transistor structure is an improvement over standard Isoplanar and is called Isoplanar II. Isoplanar II transistors eliminate the need for base region diffusion beyond the emitter ends, and for a given emitter size the collector-base junction area is less than 40 percent of the area otherwise needed for the conventional Planar transistor. The total silicon area per transistor is reduced by more than a factor of 2 over conventional IC techniques. These features reduce the collector-base and collector-isolation capacitances significantly. The result is significant improvement in switching performance without any sacrifice in voltage levels and voltage supply tolerances.read more
Citations
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Journal ArticleDOI
Gigabit electronics—A review
TL;DR: In this paper, the authors investigated the Gigabit transistors and transistors with high packing density for low interconnection delay, but power dissipation leads to limitations, which are due to the involved wide bandwidths at microwave spectral frequencies.
Journal ArticleDOI
Isoplanar integrated injection logic: a high-performance bipolar technology
TL;DR: In this paper, a newly developed technology is discussed to achieve high packing density and high performance by use of various process innovations combined with topological design variations, and the results of computer simulations and measured device parameters and power delay are given.
Proceedings ArticleDOI
A high-speed 1600-gate bipolar LSI processor
TL;DR: A SUB-NS bipolar 8-bit 1600-gate LSI processor fabricated by a Polysilicon Self-Aligned (PSA) method, combined with three-layer metalization and 120-pin gang lead bonding affording high packing density, low power consumption and high speed operation, will be described.
Journal ArticleDOI
Improved feedback ECL gate with low delay-power product for the subnanosecond region
Hans-Martin Rein,R. Ranfft +1 more
TL;DR: It will be demonstrated theoretically how to remove the hysteresis and how to optimize the transfer characteristic using emitter resistors.
Proceedings ArticleDOI
Dielectric isolation using shallow oxide and polycrystalline silicon
J.I. Raffel,S.E. Bernacki +1 more
TL;DR: In this paper, a technique was developed which combines polycrystalline isolation of collectors and shallow oxide isolation of bases, which is capable of proriding deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a combination heretofore unobtainable by any other means.
References
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Journal ArticleDOI
Collector diffusion isolated integrated circuits
TL;DR: In this paper, a simplified bipolar integrated circuit structure is described, which eliminates the need for the conventional isolation diffusion and achieves higher circuit packing densities with fewer fabrication steps than are required in fabrication of the standard buried collector structure.
Journal ArticleDOI
Epitaxial V-groove bipolar integrated circuit process
T.J. Rodgers,J.D. Meindl +1 more
TL;DR: In this paper, a four-mask "V-groove" process for the fabrication of bipolar integrated circuits has been developed, which utilizes epitaxial ν/n+n+/n-layers and anisotropic etching of \langle100\rangle silicon to eliminate the buried layer and isolation diffusions as well as the need for masking the base diffusion of the standard six-mask bipolar integrated circuit process, n-p-n transistor, resistor, and Schottky diode characteristics.
Journal ArticleDOI
Design and fabrication of subnanosecond current switch and transistors
TL;DR: It is shown that the primary parameters affecting the performance of the transistor are mobile carrier storage in the emitter-base junction; emitter crowding; stretching of the base into the collector at high forward-current densities and conductivity modulations in the active base region.
Proceedings ArticleDOI
Fully-compensated emitter-coupled logic
TL;DR: Circuits displaying low-level dependency over wide ranges of ambient temperature, typically -30 to +85° C and -4.7 V to -6.2 V, will be described.