Journal ArticleDOI
Substrate Current of Submicrometer Buried-Gate MOSFET
TLDR
In this paper, a buried-gate MOSFET was proposed for submicrometer devices, especially for 1/4 micrometer level devices, and the results of two-dimensional device simulation indicate that the buried gate shows less substrate current than conventional MOS-FET for low gate voltages and different gate voltage dependence of the substrate current.Abstract:
A buried-gate MOSFET is proposed for submicrometer devices, especially for 1/4 micrometer level devices. In this structure, reduced short channel effects are shown and very shallow junctions are not required. The results of two-dimensional device simulation indicate that the buried-gate MOSFET shows less substrate current than conventional MOSFET for low gate voltages and different gate voltage dependence of the substrate current.read more
Citations
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Patent
Process for the production of a MIS transistor with a raised substrate/gate dielectric interface end
Pierre Jeuch,Jean-Jacques Niez +1 more
TL;DR: In this article, a process for the production of a MIS transistor with a rising substrate/gate dielectric interface wall is described, where on the surface of a semiconductor substrate having a given doping type is formed a first electrically insulating layer surrounding a zone of the substrate surface.
Proceedings ArticleDOI
Self-aligned contact schemes for source-drains in submicron devices
TL;DR: In this paper, the basic limitations in source-drain parasitics and source-drone contacts as devices are scaled to the submicron regime are reviewed and various proposals to provide local interconnect layers which interface with the source-rain and from which all contact windows to metal-1 are made over field oxide.
Patent
Method of manufacturing a mis transistor with raised dielectric interface of the gate and substrate at its extremities
Pierre Jeuch,Jean-Jacques Niez +1 more
TL;DR: In this article, a first electrically insulating layer (42) is formed at the surface of a semiconductor substrate (40) having a given type of doping, this layer surrounding a zone (44) of the surface surface of the substrate; a second layer (46) is revealed by removing a fragment of the second layer, this fragment extending above this part, which thus constitutes the bottom of a hole (51) made in the first layer, and above a part of the first insulating layers a hollow is formed comprising at least one raised-up end, in the
Patent
Transistor mos a extremite d'interface dielectrique de grille/substrat relevee et procede de fabrication de ce transistor
Pierre Jeuch,Jean-Jacques Niez +1 more
TL;DR: In this article, the transistor MOS submicroniques are fabricated by using a couche isolante and a conductrice in order to former the grille of the transistors.
References
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Proceedings ArticleDOI
Enhancement of hot-electron currents in graded-gate-oxide (GGO)-MOSFETs
TL;DR: In this article, the performance of the GGO-MOSFET with various degrees of gate-drain-source overlap and grading thickness of the gate oxide near the polysilicon-gate edge has been investigated.