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Proceedings ArticleDOI

Synchronization of communicating modules and processes in high level synthesis

Santonu Sarkar, +2 more
- pp 87-92
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TLDR
This paper proposes an object oriented design framework to support reuse in ASIC designs and the steps to be taken for synchronization of communicating hardware entities through a non-blocking channel have been analyzed.
Abstract: 
In ASIC designs, reuse of already available components is often preferred. Synthesis systems catering to this need must ensure proper synchronization among the communicating modules. This paper proposes an object oriented design framework to support reuse. The steps to be taken for synchronization of communicating hardware entities through a non-blocking channel have been analyzed. The synthesis system ensures synchronization among the communicating modules before scheduling. The scheme has been tested on a few real life image processing examples.

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Citations
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Patent

Design apparatus and a method for generating an implementable description of a digital system

Patrick Schaumont, +2 more
TL;DR: In this article, the authors present a design apparatus compiled on a computer environment for generating from a behavioral description of a system comprising at least one digital system part, an implementable description for said system, said behavioral description being represented on said computer environment as a first set of objects with a first sets of relations there between, said implementable descriptions being represented as a second set of object with a second sets of relation there between.
Proceedings ArticleDOI

An efficient semaphore implementation scheme for small-memory embedded systems

Khawar M. Zuberi, +1 more
TL;DR: The authors present a new semaphore implementation scheme which saves one context switch perSemaphore lock operation in most circumstances and gives performance improvements of 18-25% over traditional semaphores implementation schemes.
Proceedings ArticleDOI

High-level synthesis of multi-process behavioral descriptions

Weidong Wang, +3 more
TL;DR: It is demonstrated that state-of-the-art high-level synthesis tools can generate significantly sub-optimal implementations for behaviors that contain concurrent communicating processes.
Proceedings ArticleDOI

The GAPLA: a globally asynchronous locally synchronous FPGA architecture

X. Jia, +1 more
TL;DR: This paper proposes GAPLA: a globally asynchronous locally synchronous programmable logic array architecture that shows an up to 28% performance improvement compared to the conventional FPGAs with small area overhead.
Patent

Reuse of hardware components

Patrick Schaumont, +2 more
TL;DR: In this article, the authors propose a method for designing an electronic system having at least one digital part, which includes representing a behavioral description of the system as a first set of objects with a first sets of relations there between.
References
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Journal ArticleDOI

Communicating sequential processes

C. A. R. Hoare
- 01 Aug 1978 - 
TL;DR: It is suggested that input and output are basic primitives of programming and that parallel composition of communicating sequential processes is a fundamental program structuring method.
Journal ArticleDOI

Synthesizing circuits from behavioural descriptions

Raul Camposano, +1 more
- 01 Feb 1989 - 
TL;DR: The authors discuss in detail the synthesis of structures from behavioural domain descriptions using a formal language, internal representation of the behaviour, synthesis based on data-flow analysis, optimizations and generation of a hardware structure.

HardwareC -- A Language for Hardware Design (Version 2.0)

David Ku, +1 more
TL;DR: A hardware description language called HardwareC is presented, which supports both declarative and procedural semantics, has a C-like syntax, and is extended with notion of concurrent processes, message passing, timing constraints via tagging, resource constraints, explicit instantiation of models, and template models.
Journal ArticleDOI

Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits

D.C. Ku, +1 more
- 01 Jun 1992 - 
TL;DR: The authors present a relative scheduling formulation that supports operations with fixed and unbounded delays and describes the generation of control logic from the resulting relative schedule.
Journal ArticleDOI

Interface optimization for concurrent systems under timing constraints

D. Filo, +3 more
- 01 Sep 1993 - 
TL;DR: In this paper, the authors describe a technique called interface matching that minimizes the interface cost by scheduling each process with respect to timing information of other processes communicating with it, while ensuring the communication remains valid.