Patent
Synchronous cache memory system incorporating tie-breaker apparatus for maintaining cache coherency using a duplicate directory
TLDR
In this paper, tie-breaker circuits detect conditions relating to a request which could result in cache incoherency, it initiates uninterrupted sequences of cycles within the corresponding cache main or duplicate directory to complete the processing of that same request.Abstract:
A multiprocessor data processing system includes a processing unit which, together with other processing units, including input/output units, connects in common to an asynchronous bus network for sharing a main memory. At least one processing unit includes a synchronous private write through cache memory system which includes a main directory and data store in addition to a bus watcher and a duplicate directory. The bus watcher connects to the asynchronous bus network and captures all main memory requests while the duplicate directory maintains a copy of the cache unit's main directory. Independently and autonomously synchronously operated tie-breaker circuits apply requests to the main and duplicate directories. When tie-breaker circuits detect conditions relating to a request which could result in cache incoherency, it initiates uninterrupted sequences of cycles within the corresponding cache main or duplicate directory to complete the processing of that same request.read more
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Patent
Transaction activation processor for controlling memory transaction processing in a packet switched cache coherent multiprocessor system
Zahir Ebrahim,Satyanarayana Nishtala,William C. Van Loo,Kevin Normoyle,Paul N. Loewenstein,Louis F. Coffin +5 more
TL;DR: In this article, the system controller includes transaction activation logic for activating each memory transaction request when it meets predefined activation criteria, and for blocking each said transaction request until the predefined activating criteria are met.
Patent
Cache coherency protocol for multi processor computer system
Darrel D. Donaldson,Mark N. Howard,David A. Orbits,John M. Parchem,David M. Robinson,Douglas D. Williams +5 more
TL;DR: In this paper, the authors propose a cache coherency protocol for multi-processor systems which provides for read/write, read-only and transitional data states and for an indication of these states to be stored in a memory directory in main memory.
Patent
System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
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Patent
Symmetric multiprocessing system with unified environment and distributed system functions
Bertone James,Diplacido Bruno,Thomas F. Joyce,Massucci Martin,Mcnally Lance,Murray Thomas L,Chester M. Nibby,Pence Michelle,Sanfacon Marc,Jian-Kuo Shen,Jeffrey Somers,Steiner G Lewis +11 more
TL;DR: A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations as discussed by the authors.
Patent
Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system
TL;DR: In this article, the bus interface is coupled to the processor, the backup cache memory and to the bus in accordance with a SNOOPY protocol to monitor transactions on the bus for write transactions affecting data items in the corresponding secondary cache memory having set VALID indicators.
References
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Patent
Cached multiprocessor system with pipeline timing.
TL;DR: In this article, the authors describe a multiprocessor data processing system including a main memory system, the processors (30) of which share a common control unit (CCU 10) that includes a write-through cache memory (20), for accessing copies of memory data without undue delay in retrieving data from the main memory systems.
Patent
Prefetching system for a cache having a second directory for sequentially accessed blocks
TL;DR: In this article, a prefetching mechanism for a system having a cache has, in addition to the normal cache directory, a two-level shadow directory, in which a parent identifier derived from the block address is stored in a first level of the shadow directory.
Patent
Apparatus for cache clearing
TL;DR: In this paper, a cache clearing apparatus for a multiprocessor data processing system having a cache unit and a duplicate directory associated with each processor is described, where commands affecting information segments within the main memory are transferred by the system controller unit to each of the duplicate directories to determine if the information segment affected is stored in the cache memory of its associated cache memory.
Patent
Eviction control apparatus
TL;DR: In this article, a translation look-aside buffer is used to translate logical addresses to system addresses and a control field includes a flipper bit for indicating which one of the system addresses is the currently active real address.