Patent
Synchronous pipeline with normally transparent pipeline stages
Reads0
Chats0
TLDR
A synchronous pipeline segment and an integrated circuit (IC) including the segment is defined in this paper, where data items pass locally asynchronously between the input and output stages and are separated by opaque gated intermediate stages.Abstract:
A synchronous pipeline segment and an integrated circuit (IC) including the segment. The segment includes an input stage, an output stage and at least one intermediate stage. A place holder latch associated with each stage indicates whether valid stage data is in the stage. A local clock buffer provides a local clock gating a corresponding stage. The input and output stages are normally opaque and intermediate stages are normally transparent. Data items pass locally asynchronously between the input and output stages and are separated by opaque gated intermediate stages.read more
Citations
More filters
Patent
Dynamic Merging of Pipeline Stages in an Execution Pipeline to Reduce Power Consumption
TL;DR: In this paper, the execution logic in successive pipeline stages in an execution pipeline may be dynamically merged together by setting one or more latches that are intermediate to such pipeline stages to a transparent state such that the output of the pipeline stage preceding such latches is passed to the subsequent pipeline stage during the same clock cycle.
Patent
Method and Apparatus for Detecting Clock Gating Opportunities in a Pipelined Electronic Circuit Design
TL;DR: In this paper, a pipeline electronic circuit and design methodology enables power conservation in the stages of the pipeline via a simulation that identifies clock-gating opportunities among the stages in the pipeline.
Patent
Transparently Increasing Power Savings in a Power Management Environment
TL;DR: In this paper, a virtualization mechanism is provided for transparently consolidating resources of logical partitions in logical partitions, where the existence of the non-folded resource on an originating resource chip is considered.
Patent
Method and system for elastic signal pipelining
TL;DR: In this article, the authors propose a method for configuring a signal path within a digital integrated circuit, which includes transmitting an output from a first logic module, receiving the output at a second logic module and conveying the output from the first one to the second one by using a configurable signal path.
Patent
Clock gated pipeline stages
TL;DR: The gated clock logic as discussed by the authors allows a clock signal to drive active stages and gates the clock signal from driving idle stages of a processor to determine whether a pipeline stage is active or idle.
References
More filters
Proceedings ArticleDOI
Synchronous interlocked pipelines
Hans M. Jacobson,Prabhakar Kudva,Pradip Bose,Peter W. Cook,Stanley E. Schuster,Eric Mercer,Chris J. Myers +6 more
TL;DR: A novel technique based on local clock gating and synchronous handshake protocols that achieves stage level interlocking characteristics in synchronous pipelines similar to that of asynchronous pipelines is presented.
Proceedings ArticleDOI
Stretching the limits of clock-gating efficiency in server-class processors
Hans M. Jacobson,Pradip Bose,Zhigang Hu,Alper Buyuktosunoglu,Victor Zyuban,Richard J. Eickemeyer,Lee Evan Eisen,John Barry Griswell,D. Logan,Balaram Sinharoy,Joel M. Tendler +10 more
TL;DR: This paper examines the realistic benefits and limits of clock-gating in current generation high-performance processors and examines additional opportunities to avoid unnecessary clocking in real workload executions, and examines the power reduction benefits of a couple of newly invented schemes called transparent pipeline clock- gating and elastic pipeline Clock-Gating.
Proceedings ArticleDOI
Pipeline stage unification: a low-energy consumption technique for future mobile processors
TL;DR: Effectiveness of PSU to DVS in current and future process generations is compared and evaluation results show PSU will reduce energy consumption by 27-34% more than DVS after about 10 years.
Proceedings ArticleDOI
Improved clock-gating through transparent pipelining
TL;DR: A new theory for optimal clocking of synchronous pipelines is presented, practical implementations are presented and the clock power benefits on a multiply/add-accumulate unit design are evaluated.
Proceedings ArticleDOI
Adaptive pipeline depth control for processor power-management
A. Efthymiou,Jim Garside +1 more
TL;DR: A method of managing the power consumption of an embedded, single-issue processor by controlling its pipeline depth is proposed, and two techniques are shown using an existing asynchronous processor as a starting point.