Patent
Synthesis of a synchronization clock
TLDR
In this paper, a two-stage interpolation system is proposed to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream.Abstract:
A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream. One aspect of the clock generator provides a two-stage interpolation system. In a first stage, two clocks are selected which accurately detect a calibration data sample. In a second stage, a single, fine-tuned, clock is synthesized by interpolating the two selected clocks.read more
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Patent
Time synchronization of multiple time-based data streams with independent clocks
TL;DR: In this article, the authors describe techniques for synchronizing multiple time-based data streams with independent clocks, where the relationships between clock rates of timing devices associated with the data streams are determined, and based on these relationships, times in at least one of the time based data streams may be translated to times in any of the other times in the other data streams despite data streams having independent clocks.
Patent
Semiconductor Integrated circuit
Yutaka Shinagawa,Takeshi Kataoka,Eiichi Ishikawa,Toshihiro Tanaka,Kazumasa Yanagisawa,Kazufumi Suzukawa +5 more
TL;DR: In this article, a semiconductor integrated circuit (SIC) has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the SIC.
Patent
Memory devices, systems and methods employing command/address calibration
TL;DR: In this article, a memory controller may transmit multiple cycles of test patterns as signals to a memory device, each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device.
Patent
DDR interface for reducing SSO/SSI noise
TL;DR: An improved DDR interface uses single-ended technology and phaseshifts all output data signals and the output source clock signal so that each output signal switches at a different time so that IDDQ spikes caused by I/O switching do not accumulate.
Patent
A variability-aware scheme for high-performance asynchronous circuit voltage regulation
TL;DR: In this paper, a system for automatically transforming a given synchronous circuit description into an equivalent and provably correct desynchronized circuit description is presented, using a two-phase protocol.
References
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Patent
Semiconductor integrated circuit
TL;DR: A semiconductor integrated circuit comprising a plurality of blocks the included circuit components, where the blocks are separated from each other in a semiconductor substrate, is described in this article, where horizontal and verticle wires along the horizontal and vertical lines of an imaginary wiring grid established in a wiring region between the blocks and diagonal wirings are provided in the process of producing the blocks.
Patent
Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing
TL;DR: In this paper, a voltage controlled delay circuit with the same structure as a PLL circuit is proposed to optimize data input timing in a controller which always has a constant delay amount regardless of a change in operating environment.
Patent
Method for generating digital communication system clock signals & circuitry for performing that method
TL;DR: In this paper, a clock generating circuit generates 2n clocks, each having 1/2n frequency of a maximum baud rate of data bit stream input and a phase difference of π/n between successive phases thereof, and simultaneously shifts the phases on the clocks ahead or behind until the phases between the clocks and corresponding data bits of the data bit-stream input are locked in quadrature.
Patent
High order digital phase-locked loop system
TL;DR: In this paper, a digital data separator is used to separate data pulses from clock pulses in MFM encoded signals read from a magnetic disk system, including a digital phase-locked loop system incorporating a variable length shift register which functions as a variable oscillator and programmed state machines which control the operation of the shift register and provide filtering functions.
Patent
Retiming circuit and method for performing retiming
TL;DR: In this paper, a retiming circuit with a clock at a center portion of input data and performing correct discrimination of logic "1" and "0" even if there is duty fluctuation of a pulse, provided with delay unit for imparting a variable delay to input data or a clock.