Patent
System and method for sequencing packets for multiprocessor parallelization in a computer network system
Tai-chien Daisy Chang,Herman Dietrich Dierks,Satya Prakesh Sharma,Helmut Cossmann,William James Hymas +4 more
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TLDR
In this paper, the authors proposed a high priority queueing mechanism for network input processing on multiprocessor systems to improve network throughput and take advantage of MP scalability, where packets received on the network are distributed to N high priority threads, wherein N is the number of CPUs on the system.Abstract:
Network input processing is distributed to multiple CPUs on multiprocessor systems to improve network throughput and take advantage of MP scalability. Packets received on the network are distributed to N high priority threads, wherein N is the number of CPUs on the system. N queues are provided to which the incoming packets are distributed. When one of the queues is started, one of the threads is scheduled to process packets on this queue at any one of the CPUs that is availableat the time. When all of the packets on the queue are processed, the thread becomes dormant. Packets are distributed to one of the N queues by using a hashing function based on the source MAC address, source IP address, or the packet's source and destination TCP port number, or all or a combination of the foregoing. The hashing mechanism ensures that the sequence of packets within a given communication session will be preserved. Distribution is effected by the device drivers of the system. Parallelism is thereby increased on network I/O processing, eliminating CPU bottleneck for high speed network I/Os, thereby improving network performanceread more
Citations
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References
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Patent
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Technique for maintaining prioritization of data transferred among heterogeneous nodes of a computer network
Steven H. Berl,Kushal A. Patel +1 more
TL;DR: In this article, a technique maintains priority of packets transmitted over a heterogeneous network by a hybrid node coupled to the network by assigning each packet a transmission priority (TP) level as it traverses protocol layers of a communications stack of the node.
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TL;DR: In this paper, a processor complex architecture is proposed to facilitate accurate passing of transient data among processor complex stages of a pipelined processing engine, where the data mover circuitry cooperates with the context memories and memory manager to provide a technique for efficiently passing data among the stages in a manner that maintains data coherency in the processing engine.
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Method and system for scheduling queued messages based on queue delay and queue priority
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