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Open AccessJournal ArticleDOI

The Illinois Pattern Recognition Computer-ILLIAC III

TLDR
The Pattern Articulation Unit is the first modular parallel processor which is capable of more reliable visual identification than part analog/part digital preprocessors of much less generality and potential virtuosity and can serve as a prototype to a new generation of parallel computers that will capitalize upon thin film and integrated semiconductor circuitry of the immediate future.
Abstract
This report describes the system design of an all-digital computer for visual recognition. One processor, the Pattern Articulation Unit (PAU), has been singled out for detailed discussion. Other units, in particular the Arithmetic Unit and the Taxicrinic Unit, are treated in reports listed in the bibliography. The PAU has been shown to be a processor of fundamentally new design-its logical organization has no analog in the central processing unit of existing computers. The PAU is the first modular parallel processor which because of its digital organization is capable of more reliable visual identification than part analog/part digital preprocessors of much less generality and potential virtuosity; is faster than any presently suggested alternative realizable today at comparable cost; and can serve as a prototype to a new generation of parallel computers that will capitalize upon thin film and integrated semiconductor circuitry of the immediate future.

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Patent

Basic cell for triggering spatio-temporal pulse and pattern recognition apparatus using this cell

TL;DR: In this article, a time input and space output data are input into a calculation circuit to obtain the time output data from the time input data and space input data, and the calculation circuit uses the above-mentioned time inputs and space inputs as time outputs after inverting it or as it is, without inversion, depending on whether or not the sum of all the space inputs is larger than a threshold value.
Book ChapterDOI

Chapter VII – CELLULAR LOGIC

TL;DR: The theory of logical design with cellular logic arrays is presented in this paper, where mathematical models of some of the simple cullular structures are studied and synthesis algorithms for arbitrary switching functions are developed.
Journal ArticleDOI

Pattern recognition problems in bubble chamber physics

TL;DR: The data extraction process for bubble chamber film is described from a pattern recognition viewpoint and major problem areas and semi-automatic measuring devices are discussed.
Journal ArticleDOI

Using emulations to enhance the performance of parallel architectures

TL;DR: The potential of techniques and results from the theory of network emulations to enhance the performance of a parallel architecture and the creation of the word-parallel instruction sets-on arrays of any regular network topology is illustrated.