Time Sliced Optical Burst Switching
Jeyashankher Ramamirtham, Jonathan Turner,
{jai,jst}@arl.wustl.edu,
Computer Science and Engineering Department,
Washington University in St. Louis,
St. Louis, MO-63130
Abstract— Time Sliced Optical Burst Switching is a proposed
variant of optical burst switching, in which switching is done in the
time domain, rather than the wavelength domain. This eliminates
the need for wavelength converters, the largest single cost compo-
nent of systems that switch in the wavelength domain. We examine
some of the key design issues for routers that implement time sliced
optical packet switching. In particular, we focus on the design of
the Optical Time Slot Interchangers (OTSI) needed to effect the
required time domain switching. We introduce a novel nonblock-
ing OTSI design and also show how blocking OTSIs can be used
to implement the required switching operations. We study the per-
formance of systems using blocking OTSIs and demonstrate that
near ideal statistical multiplexing performance can be achieved us-
ing even quite inexpensive, blocking OTSI designs. These results
suggest that optical technology may one day be able to provide a
cost-effective alternative to electronics in packet switching systems.
Index Terms—burst switching, optical networking, time-slot in-
terchangers
I. INTRODUCTION
Wavelength Division Multiplexing (WDM) has made it pos-
sible to harness the enormous bandwidth potential of fiber in a
cost-effective way and is thus, becoming the method of choice
for information transmission in data networks. Systems with
hundreds of wavelengths per fiber and transmission rates of 10-
40 Gbps per wavelength are becoming available, leading to a se-
rious disparity between electronic switching speeds and optical
transmission capacity. All-optical switching seeks to eliminate
electronic switching and switch the data in its optical form, thus
eliminating the opto-electronic components which contribute a
large fraction of the cost of electronic routers. Optical switch-
ing has other potential benefits, including bit-rate independence,
protocol transparency, and low power consumption.
Optical Burst Switching [1] is an experimental network tech-
nology that seeks to use optical switching for the data path, while
still retaining the flexibility of electronics for control. To pro-
vide good statistical multiplexing performance, burst switching
and other forms of optical packet switching [2], [3], [4] require
either large optical buffers or optical wavelength converters. The
only practical optical buffers today are optical delay lines, which
are too expensive to use in the large quantities needed for opti-
cal IP routers (IP routers require buffer capacities that are com-
parable to the product of the link bandwidth and the network
This work is supported by the Advanced Research Projects Agency and Rome
Laboratory (contract F30602-97-1-0273)
round trip delay). Burst switching seeks to eliminate most opti-
cal buffering by using wavelength converters to allow dynamic
selection from a large number of wavelengths. Unfortunately,
optical wavelength conversion remains expensive, and there are
no realistic expectations that it will become inexpensive enough
to allow optical burst switches to be cost-competitive with elec-
tronic routers.
Time Sliced Optical Burst Switching (TSOBS) is a proposed
variant of optical burst switching that replaces switching in the
wavelength domain with switching in the time domain. While
time-domain switching does require the use of optical buffers,
the amount of storage needed is less than 1% of that needed for
conventional packet switching, greatly changing the cost trade-
offs. Like burst switching, TSOBS separates burst control infor-
mation from burst data. Specifically, Burst Header Cells (BHC)
are transmitted on separate control wavelengths on each WDM
link. These wavelengths are converted to electronic form at each
switch, while all remaining wavelengths are switched through
in optical form. The data wavelengths carry information in a
Time-Division Multiplexed (TDM) format, consisting of a re-
peating
frame
structure, which is sub-divided into time slots of
constant length. A repeating sequence of time slots in successive
frames, at a fixed position within the frame is referred to here, as
a channel. Each BHC “announces” the imminent arrival of a data
burst, and includes address information plus the wavelength and
channel on which the burst is arriving. It also includes an offset,
which identifies the frame in which the first timeslot contain-
ing data from the burst appears, and a length, which identifies
the number of timeslots used to transmit the burst. The proposed
combination of wavelength and time-division switching has been
studied previously in a circuit-switching context [5], [6], [7], but
we are not aware of any prior attempts to apply this approach in
a packet or burst switching context.
Optical Time Slot Interchangers (OTSI) are key building
blocks of routers in TSOBS networks. Three key factors that
affect the cost and performance of an OTSI are (1) the size of
its internal crossbar, (2) the amount of fiber required for the de-
lay lines used to reorder the timeslots, and (3) the number of
switching operations that bursts may be subjected to when pass-
ing through the OTSI. In this paper, we present an overall archi-
tecture for a TSOBS router and study how alternative OTSI de-
signs affect its cost and performance. We consider both blocking
and non-blocking OTSIs and study how different designs affect
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Frame of
time slots
Concentrator
Lower bit-rate host
interface
(e.g. Gig-Ethernet)
Packet from
a host
WDM links
Fig. 1. Time-sliced packet switched network architecture
the system’s overall statistical multiplexing performance, using
simulation.
The rest of the paper is organized as follows. In Section II,
we discuss the overall design issues for TSOBS networks. In
Section III, we present an architecture of a TSOBS router and
present alternate OTSI designs. We present simulation results for
a system using a blocking OTSI design in Section IV. Finally,
we present some concluding remarks in Section V.
II. D
ESIGN ISSUES FOR TSOBS NETWORKS
Fig. 1 illustrates the concept of a time-sliced optical burst
switched network. Switches are connected with WDM links
with multiple wavelength channels carrying data. The informa-
tion sent on each wavelength is organized into a series of frames,
each of which is sub-divided into fixed length timeslots.Termi-
nals and/or other networks connect to a TSOBS network through
concentrators that convert data on lower speed interfaces (e.g.
IP-over-Ethernet at 100 Mb/s or 1 Gb/s), to the TSOBS data for-
mat. Concentrators transmit user data bursts in time-division
channels. The control information needed to switch the data
bursts is sent in Burst Header Cells (BHC), which are carried on
separate control wavelengths. A given fiber optic link may con-
tain multiple control wavelengths. If the ratio of the expected
burst length to the BHC length is L, each link will require about
one control wavelength for every L − 1 data wavelengths. Con-
centrators may switch packets received on low speed interfaces
as single bursts in the TSOBS network, or may aggregate pack-
ets to form larger bursts. Aggregation increases the average burst
length on the TSOBS links, improving efficiency and reducing
the amount of control processing required.
The switching of data bursts through a TSOBS network is
done entirely in the optical domain. Space-division optical
switches are dynamically configured to switch the data from in-
coming timeslots to timeslots on the appropriate outgoing links.
This is done using carefully-timed switching operations to trans-
fer user data bits from input links to output links. Switching
a timeslot may involve delaying the data, to shift it from one
timeslot position to another. Frames transmitted on different
wavelengths are synchronized with one another, allowing the
Guard time
Data
t
1
t
2
t
3
t
4
t
N
Frame with N time slots
Fig. 2. Format of a frame and a time slot within it
timing of switching operations on the data wavelengths to be
determined from the frame timing on the control wavelengths.
Solid-state optical switches can perform switching operations
with a precision of 10 ns or less. To allow for timing uncertain-
ties, timeslots must be separated by a guard time of at least 10
ns and possibly as large as 100 ns. To achieve reasonable data
transmission efficiencies, timeslot durations should be at least
ten times the guard time, or 100 ns to 1 µs. A 1 µs time slot
would allow roughly 1100 bytes of user data to be sent in a sin-
gle time slot, assuming a transmission rate of 10 Gb/s per wave-
length, or 4400 bytes of user data, assuming a transmission rate
of 40 Gb/s. With a 1 µs timeslot duration and 40 Gb/s transmis-
sion speeds, a system with 350 timeslots per frame would sup-
port an individual channel rate of about 100 Mb/s. This would
correspond to a frame duration of 350 µs. This is the maximum
period that a timeslot would have to be delayed when passing
through a TSOBS router. By contrast, a conventional router may
have to delay data by hundreds of milliseconds in order to pro-
vide acceptable performance, requiring very large amounts of
data storage. Of course, a shorter timeslot duration or a smaller
number of timeslots per frame would allow this maximum delay
for a TSOBS router to be reduced proportionally.
In a large TSOBS network, bursts may pass through many
hops before reaching their destination, leading to excessive
degradation of the optical signal [8]. To avoid the need for strict
limits on the number of hops and/or the distance traveled by
bursts, we provide for periodic regeneration of bursts. This is
done by including fields in the BHC, which record the distance
traveled by a burst since its last regeneration and the number
of optical switching operations that the burst has been subjected
to since its last regeneration. This information can be used to
regenerate bursts as necessary, as they pass through a large net-
work. Each switch includes some small number of either all
optical or opto-electronic regeneration circuits that bursts can
be passed through when regeneration is needed. If bursts can
travel through an average of ten or more routers before requiring
regeneration, TSOBS could achieve a decisive cost advantage
over electronic routers. Since each switch operation that a burst
is subjected to attenuates the signal and adds noise, it is impor-
tant to minimize the number of switching operations required by
each router. The number of switching operations is hence a key
metric for TSOBS router designs.
TSOBS has been designed to make wavelength conversion un-
necessary. At the same time, the overall architecture does not
preclude the switching of bursts to different wavelengths, should
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1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
Input Load
Discard Probability
N =2
S =16
64
128
32
16
8
4
Fig. 3. Packet discard probability for a system with 16 sources and different
frame times (N )
wavelength conversion become inexpensive enough to make this
practical.
The statistical multiplexing performance of a TSOBS network
is determined primarily by the number of timeslots per frame.
For simplicity, we focus here on the case of simple multiplexor
that corresponds to a S ×1 switch receiving bursts from S input
channels that can be accommodated by a single timeslot. If the
multiplexor assigns each arriving burst to the first available out-
going timeslot, the multiplexor operates like an M/D/1 queueing
system with a buffer capacity of N, where N is the number of
timeslots per frame.
Fig. 3 shows the burst discard probabilities for a multiplexor
with various values of N. Notice that the discard probability
drops very quickly with N, but increases beyond a certain point
yielding diminishing returns. 32 timeslots is sufficient to main-
tain a discard probability of 10
−6
at an offered load of about
83%. Doubling N increases the load at which this target dis-
card probability is reached to about 92%. Variable length bursts
lead to higher discard probabilities, but the number of timeslots
per frame remains the key determinant of performance. This
illustrates the central trade-off for TSOBS networks. While in-
creasing the number of timeslots per frame improves the statis-
tical multiplexing performance, this improvement comes at the
cost of longer frame durations, which translates to larger optical
buffering requirements. In Section IV we look in more detail at
the performance of a TSOBS router, using simulation.
III. S
WITCH ARCHITECTURE
A. Overview
Fig. 4 shows the overall design for a TSOBS router. Each in-
coming WDM link terminates on a Synchronizer (SYNC) which
synchronizes the incoming frame boundaries to the local timing
reference. This is done using variable delay lines, with feed-
back control of the delays being provided through the system
controller. The synchronizers are followed by Optical Time Slot
Interchangers (OTSI), which provide the required time domain
Optical
Crossbar
Controller
OTSI
OTSI
Optical
Crossbar
WDM Links
. . .
. . .
λ
1
λ
h
λ
1
λ
h
BHCs
control signals
SYNC
SYNC
WDM multiplexor
Fig. 4. The overall Time-Sliced Optical Burst Switch design
switching for all wavelengths. The OTSIs also separate the con-
trol wavelengths carrying the BHCs and forward those to the
system controller. In addition the input OTSIs separate the data
wavelengths and forward these on separate fibers to each of a set
of Optical Crossbars at the center of the diagram. The crossbars
perform the required space division switching operation. These
are followed by a set of passive optical multiplexors, which com-
bine the data wavelengths with the control wavelengths (carrying
the outgoing BHCs) on the output fibers. The controller uses the
information in the BHCs to make switching decisions and gen-
erates electronic control signals which are used to control the
operation of the OTSIs and the crossbars.
Fig. 5 shows a high level design for one of the OTSIs. Each
OTSI contains a set of optical crossbars for switching timeslots
among the inputs, outputs and a set of delay lines. The signals
are demultiplexed to perform the switching operations and re-
multiplexed onto the delay lines, allowing the cost of the delay
lines to be shared by the different wavelengths. The number
of delay lines and the choice of delay line values are key design
parameters, significantly affecting both the cost and performance
of the OTSI.
B. Nonblocking OTSIs
We can classify OTSI designs as either blocking or nonblock-
ing. While nonblocking designs provide the best performance,
they are significantly more expensive than blocking designs. We
start with the conceptually simplest nonblocking design, which
has N delay lines with a delay value equal to the duration of one
time slot. With this design, each incoming timeslot i can be de-
layed by d timeslot intervals by recirculating it through the ith
delay line d times. Since each timeslot is assigned to a separate
delay line, there are no conflicts, hence the design is nonblock-
ing. It also uses the smallest possible total delay line length (N ,
where the unit is the distance light propagates in one timeslot
interval). Unfortunately, it requires a large number of separate
delay lines (N ) and large optical crossbars ((N +1)×(N +1)).
The optical crossbars are a particular concern since their cost
grows as the product of the number of inputs and outputs. Fi-
nally, the design can subject a signal to up to N optical switch-
ing operations, causing excessive degradation to the optical sig-
nal quality, when N is large. This last fault can be corrected by
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Optical
Crossbar
WDM
input
. . .
BHCs to Controlle
r
Optical
Crossbar
. . .
delay
lines
to
central
crossbars
λ
1
λ
h
demux
Fig. 5. Optical Timeslot Interchanger
replacing the delay lines of length 1, with delay lines of length
1, 2,...,N. This allows each timeslot to be switched through
just a single delay line, reducing the number of switching oper-
ations to 2. Of course, it comes at the cost of increasing the total
delay line length from N to approximately N
2
/2.
A more practical nonblocking switch design uses delay lines
of length 1, 2, 3,...,(A − 1), where A is an integer parameter,
plus additional delay lines of length A, 2A, 3A,...,(B − 1)A
time slots, where B is a second integer parameter. We call these
two sets of delay lines the short delay lines and the long delay
lines. Let us suppose a time slot has to be delayed by a value
of T time slots. T can be expressed as a sum, k
2
A + k
1
, where
k
1
∈ [0,A) and k
2
∈ [0,B). To delay the time slot by T , we pass
the data through the long delay line of length k
2
A and then pass
it through the short delay line of length k
1
. The maximum we
can delay a signal using this configuration is (B −1)A+(A−1)
and since the maximum delay needed is N − 1, this gives us the
relation AB ≥ N. The number of delay lines in this design
is A + B − 2 and hence, choosing A = B =
√
N gives us
the minimum number of delay lines. It can be easily seen that
these values of A and B generate all values between 0 and N
because k
1
and k
2
are the digits of T when expressed in base
√
N notation.
We next show that this design is nonblocking. Consider any
two input timeslots i and j that are to be delayed by amounts d
i
and d
j
, where i + d
i
= j + d
j
. Suppose first that d
i
/A =
d
j
/A. Then both time slots will pass through the same long
delay line, but since they arrive at different times, they will
emerge from the delay line at different times. Hence, they can-
not conflict with each other when entering a short delay line.
Since i + d
i
= j + d
j
, they must emerge from the short de-
lay lines at different times, ensuring no conflict at the output.
Now suppose that d
i
/A = d
j
/A. In this case, the time slots
may emerge from their respective long delay lines at the same
time, creating a potential conflict if they must be switched to the
same short delay line. However, such a conflict can only occur
if i + d
i
= j + d
j
, contradicting the condition on the overall de-
lays. Hence, the design is nonblocking, assuming timeslots are
always switched first through a long delay line, then through a
short delay line.
The size of the crossbar required for this design is (2
√
N−
1) ×(2
√
N−1) (31 ×31 for N = 256) and the length of the
fiber required is N
√
N/2 (2,048 when N = 256). Thus, we
have reduced the size of the crossbar at the expense of increased
fiber length, relative to the first design. This design also limits
the number of switching operations that a timeslot is subjected
to, to at most three. Also note that it is very easy to determine
the switching operations needed to switch a timeslot.
References [9] and [10] describe a timeslot interchanger de-
sign that is rearrangeably nonblocking meaning that it can be
configured to permute a set of N timeslots in an arbitrary way,
assuming that the required permutation is given in advance. This
approach can be implemented using two set of delay lines of
length 1, 2,...,N/4 and a single delay line of length N/2,
where N is assumed to be a power of 2. This gives 2(log
2
N)−1
delay lines and a total delay line length of (3N/2) − 2.Onthe
other hand, it requires 2(log
2
N) − 1 switching operations (15
for N = 256) and it requires that the full permutation be known
in advance, or that the entire switch configuration be changed
as new timeslots are received, making it difficult to apply in the
TSOBS context.
Table I summarizes the four nonblocking TSI designs dis-
cussed above and shows their complexity characteristics. Only
the third design is a real candidate for practical use, and even it
is somewhat expensive, both in terms of total fiber length and
crossbar complexity.
C. Blocking OTSIs
Blocking OTSIs are an alternative to nonblocking OTSIs, of-
fering lower complexity, at the cost of some small non-zero
blocking probability. In the TSOBS context, the impact of a
blocking TSI will be to reduce the statistical multiplexing per-
formance slightly.
Perhaps the most natural choice of delays for a blocking TSI
is the set {1, 2, 4,...,N/2}. This allows any time-slot to be
switched to any of the output timeslots, provides small total de-
lay (255 for N = 256) and small crossbar size (8×8 for N=256).
We show below that an OTSI with these delays can be operated
so as to achieve a small average number of switching operations
(≤ 3 under most conditions), and that the impact of blocking on
the statistical multiplexing performance is very small.
For a blocking TSI, we need to define a search procedure to
find a sequence of delay lines through which we can switch an
arriving timeslot, to deliver it to a free output timeslot. This
needs to be done without creating any conflicts at any of the de-
lay lines. The key to implementing the search procedure is a
schedule that allows us to keep track of which delay lines are
available for use at each point in time. The schedule is repre-
sented by an array of bits, sched[i, t] with k +1rows and mN
columns, where k is the number of delay lines, N is the number
of timeslots per frame and m is an upper bound on the number
of timeslots that can be used for a single burst. For i ∈ [1,k],we
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Delay line lengths Crossbar Size Fiber Length (in timeslots) Switching Operations
N = 256 N = 256 N = 256
N ×1 N +1 257 N 256 N 256
1, 2,...,N − 1 N 256 N
2
/2 32896 2 2
1,...,A,2A,...,(B − 1)A 2
√
N−1 31 N
√
N/2 2048 3 3
2 ×(1, 2, 4,...,N/4),N/2 2 log
2
N 16 (3N/2) − 2 382 2(log
2
N) − 1 15
Blocking TSI: 1, 2,...,N/2 log
2
N 8 N −1 255 variable 2to3
TABLE I
TABLE SHOWING THE COMPLEXITY OF THE TSI DESIGNS
let sched[i, t]=1if the ith delay line is “busy” at time t.We
say a delay line is busy at a given time, if there is some timeslot
scheduled to exit the delay line at that time. For simplicity, we
define t =0to be the current time. We let sched[0,t]=1if the
output link of the OTSI is busy at time t.
Fig. 6 shows an example of the schedule array for k =3,
N =8and m =1. The delay values for each of the delay
lines are shown next to their rows. The schedule array implic-
itly defines a directed graph G =(V,E) that can be used to
find a sequence of delay lines leading to a free output times-
lot, that can be used for an arriving burst. The vertex set V ,is
{u
0
,...,u
N−1
}. Each vertex corresponds to a potential delay
that a timeslot may be subjected to. The set of edges E consists
of all pairs (u
i
,u
j
) for which there is some delay line h with
delay j − i, and sched[h, j]=0. Fig. 7 gives an example of the
graph defined by the schedule in Fig. 6.
To find the best sequence of delay lines, we essentially per-
form a breadth-first search on this graph, starting from node u
0
.
Such a search constructs a shortest path tree in the graph, as il-
lustrated in Fig. 8. The unshaded nodes have delay values that
correspond to free timeslots on the output link. The path in the
tree to such an output defines a sequence of delay lines that can
be used to reach that output. The delay line corresponding to an
edge (u
i
,u
j
) on such a path, is the delay line with delay value
j − i. The number of switching operations is minimized by se-
lecting a path of minimum length from u
0
to an unshaded ver-
tex. When there are two or more unshaded vertices on minimum
length paths from u
0
, we select the vertex u
i
with the small-
est value of i, in order to minimize the delay that a timeslot is
subjected to. In Fig. 8, u
3
is selected at the conclusion of the
search, and the timeslot is then switched through the delay lines
of length 1 and 2.
The search can be done using the schedule array. The proce-
dure does construct the shortest path tree, but does not explicitly
construct the graph. A code fragment implementing the required
search procedure is shown below. In this procedure, q is a list of
nodes from which the breadth-first search needs to be extended
next, p(u
i
) is the parent of u
i
in the shortest path tree constructed
by the search procedure and n(u
i
) is the number of edges on the
path from u
0
to u
i
in the tree. The variables δ
1
<δ
2
< ···<δ
k
are the k different delay values and s is the number of timeslots
that the burst being scheduled requires.
delay 1
delay 2
delay 4
output
01234567
indicating delay
line is “busy”
indicating output
link is “busy”
Fig. 6. Example of the schedule array for k =3, N =8and m =1
q := [u
0
];
p(u
i
):=Øfor all i;
n(u
i
):=∞ for all i;
b := −1;
while q =[]do
u
i
:= q[1]; q := q[2..]; // remove u
i
from q
if sched[0,d(u
i
)] = 0 then
if b = −1 or
n(u
i
) <n(u
b
) or
n(u
i
)=n(u
b
) and i<bthen
b := i;
end;
end;
for h =1to k loop
Let u
j
be the vertex with j = i + δ
h
;
if sched[h, j]=0
and n(u
i
)+1<n(u
j
) then
p(u
j
):=u
i
; n(u
j
):=n(u
i
)+1;
if u
j
∈ q then
q := q &[u
j
]; // add u
j
to q
end;
end;
end;
end;
When a search terminates successfully, b is the delay value
associated with the selected output timeslot. If the path from
u
0
to u
b
(defined by the parent pointers) goes through nodes
u
0
= u
i
1
,u
i
2
,...,u
i
r
= u
b
the timeslot is switched through
the delay lines with delay values i
2
− i
1
,i
3
− i
2
,...,i
r
− i
r−1
.
The schedule must be updated to indicate the busy status of the
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