Book ChapterDOI
Vector Computer Architecture and Processing Techniques
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The chapter describes the architectures of recently developed SIMD array processors and examines the development experiences of the Burroughs Scientific Processor (BSP) and the Goodyear Aerospace Massively Parallel Processor (MPP).Abstract:
Publisher Summary Vector- or array-processing computers are essentially designed to maximize the concurrent activities inside a computer and to match the bandwidth of data flow to the execution speed of various subsystems within a computer. This chapter reviews architectural advances in vector-processing computers. It describes the two major classes of vector machines—namely, the pipeline computers and array processors. Problems associated with designing pipeline computers are also presented with examples from the Texas Instruments Advanced Scientific Computer (TI-ASC), Control Data STring ARay (STAR-100) and CYBER-205 Computers, Cray Research CRAY-1, and Floating-Point Systems AP-120B. The chapter describes the architectures of recently developed SIMD array processors. Further, it examines the development experiences of the Burroughs Scientific Processor (BSP) and the Goodyear Aerospace Massively Parallel Processor (MPP). Recent research works on array and pipeline processors are also summarized. The chapter concludes with the evaluation of the performance of pipeline and array processors and explores various optimization techniques for vector operations. Hardware, software, and algorithmic issues of vector-processing systems and future trends of vector computers are also discussed.read more
Citations
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Partitioned Matrix Algorithms for VLSI Arithmetic Systems
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TL;DR: A new class of partitioned matrix algorithms is developed for possible VLSI implementation of large-scale matrix solvers that can be applied to solve arbitrarily large linear systems of equations in an iterative fashion.
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A VLSI Systolic Architecture for Pattern Clustering
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Proceedings ArticleDOI
Detecting pipeline structural hazards quickly
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References
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Journal ArticleDOI
Some Computer Organizations and Their Effectiveness
TL;DR: A hierarchical model of computer organizations is developed, based on a tree model using request/service type resources as nodes, which indicates that saturation develops when the fraction of task time spent locked out approaches 1/n, where n is the number of processors.
Journal ArticleDOI
Parallel Processing with the Perfect Shuffle
TL;DR: Given a vector of N elements, the perfect shuffle of this vector is a permutation of the elements that are identical to aperfect shuffle of a deck of cards.
Journal ArticleDOI
Access and Alignment of Data in an Array Processor
TL;DR: This paper discusses the design of a primary memory system for an array processor which allows parallel, conflict-free access to various slices of data, and subsequent alignment of these data for processing, and a network based on Stone's shuffle-exchange operation is presented.
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TL;DR: A systolic system is a network of processors which rhythmically compute and pass data through the system, and almost all processors used in the networks are identical, so that a regular flow of data is kept up in the network.