Showing papers on "Adder published in 1968"

Ternary arithmetic unit

Abstract: A ternary arithmetic unit is proposed which is based on the ternary symmetric number representation using digit +1, 0, −1. The advantages of this number representation are given in detail. Present-day familiar diode-transistor circuitry is applied. Detailed circuit realisations and logic diagrams of ternary gates, a 3-stable element, and a ternary full adder are developed.

Method and devices for converting coded binary signals into multilevel signals and for reconverting the latter into the former

Abstract: Code converter for converting a first sequence of coded binary signals xeach of said signals being formed of m bits, having a given duration and being capable of taking 2m possible values, into a second sequence of multilevel signals zn whose amplitude has (2m 1- 1) possible levels proportional to the series of integers from - (2m- 1) to + (2m- 1) including zero The converter comprises a register for supplying the signals xn of the first sequence, a modulo p adder circuit where p 2m having a first input connected to the register and a second input, said modulo p adder circuit generating a third sequence of m-bit binary signals yn, a nonborrow subtractor circuit having a first input being connected to the output of said adder circuit and a second input, a delay circuit having an input connected to the output of the adder circuit for delaying said signals yn by the duration of the signals xn and thereby delivering the signals yn1 at the time of occurence of the signal xn and an output connected to the second input of both said adder circuit and subtractor circuit The nonborrow subtractor circuit provides a sequence of m-digit signals whose digits are - 1, 0 and + 1 Each digit of said m-digit signals is multiplied by a coefficient equal to the weight thereof to obtain multilevel components relative to each of said digits and these components are algebraically added Means for reconverting the multilevel signals zn into the coded binary signals xn are also described

Division system and method

Abstract: A system and method for digital division employing a composite of table lookup and iteration techniques. A stored logic table is used which generates a factor M which when multiplied against the divisor, provides a new divisor in a predetermined range close to unity in value. Both the divisor and the dividend are then multiplied by the factor M, the capacity of the table lookup determining the maximum difference of the new divisor from unity. The arrangement is such that, depending upon the difference between the new divisor and unity, a selected number of new partial quotient digits is directly determined from a selected number of digits in newly generated partial remainders. By generating quotient digits in successive groups, only a few iterations are needed to divide one long number by another. Successive division steps entail merely the generation of new partial products, and derivation of the difference of these partial products from the previous partial remainder. By arranging the significant portion of the new divisor to be a negative quantity in a preferred form of system, only adder circuits need by employed. A high speed, high capacity binary digital division system utilizing these techniques is further arranged to utilize carry-save adder circuits to utilize carry and sum quantities without introducing carry propagation delays, and otherwise minimize operating cycle time.

Data processing system capable of operation despite a malfunction

Abstract: An electronic data processing machine wherein various functional units such as the adder and certain registers may be utilized at one-half or a lesser fraction of their normal operating capability. Upon detection of an error in one of said functional units, the system will determine whether one-half of the unit is functioning properly. Data will be sent through the properly functioning half of the unit in two or more passes to perform the same operation that would have been performed in one pass if there had been no malfunction. Upon termination of the error condition the unit is automatically returned to its normal operating mode.

Arithmetic unit utilizing magnetic core matrix registers

Abstract: A compact computer of the serial type using magnetic memory devices as registers with one register being connected to an indicating device for immediate external indication. By using the memory devices in an improved manner with buffer registers, the alternative readout and storage procedures are avoided and addition or subtraction of binary coded decimal numbers can be performed during the readout period and thereby reduce processing time. The computer also enables the application of a correction signal to the adder or subtractor during write-in and does not require a separate binary adder or subtractor. Left and right shift operations are simplified and when the value stored in the memory device is read out starting with the most significant position, one flip-flop is set by the most significant digit and the output is fed to an indicating tube. This eliminates the need for indicating meaningless zeros.

Serial bcd adder/subtracter/complementer utilizing interlaced data

Abstract: A serial digital adder/subtracter/complementer for binary coded decimal data presented in interlaced format. The data at each input comprises a series of multidigit decimal words interlaced by serially presenting the least significant digit of each word in predetermined sequence, followed by the next digit of each word similarly interlaced and so on throughout the data. The adder/subtracter/complementer utilizes a first full adder/subtracter for adding or subtracting the input data. The system allows selection of either addition or subtraction and, when subtracting, designates the minuend and subtrahend. The output of the first full adder is passed through three bits of delay to one input of a second full adder/subtracter. As each digit is manipulated, it is examined to see if an incorrect result, i.e., a sum in excess of nine or a negative difference has been generated. If so, the number six (6) in binary coded decimal is fed to a second input of the second adder/subtracter where it is added to or subtracted from the output of the first adder/subtracter to accomplish the necessary correction from binary to binary coded decimal. The second full adder/subtracter is modified so as to permit generation of the two''s complement of a BCD digit applied at its input.

Design for a full multiplier

Abstract: A cellular array is described which has the property of multiplying two binary numbers, and also of adding either one or two other numbers. The array can be extended to any number of bits. It is proposed that this array might be considered as a full multiplier, analogous to a full adder. Some applications of the array are mentioned. These include the synthesis of a quadratic equation, extracting a square root and obtaining a reciprocal of a binary number.

High-speed computer logic with gunn-effect devices

Abstract: The application of the Gunn effect for fast logic circuits is discussed. In particular, several new devices, such as comparators, which rely on the possibility of domain-nucleating control are described. The ultimate time-constants of these new devices can be at least one order of magnitude better than the most advanced monolithic structures with conventional transistor and diode circuitry. Finally, two circuits, namely, an adder and a shift register, incorporating these new Gunn-effect devices are proposed.

Versatile multiplier arrays

Abstract: Recent letters have described two multiplier arrays. It is now proposed that these arrays are more versatile than was formerly supposed. They can be used both as multipliers and as adders, either separetely or together, giving a parallel binary output.

Serial bcd adder/subtracter utilizing interlaced data

Abstract: A serial digital adding/subtracting arrangement for binary coded decimal data presented in interlaced format. The input data comprises a series of multidigit decimal words interlaced by serially presenting the least significant digit of each word in predetermined sequence, followed by the next digit of each word similarly interlaced, and so on throughout the data. The adding/subtracting utilizes two full adder/subtracters, the first for adding or subtracting the input data, the second for adding or subtracting six to or from the sum or difference generated by the first. The presence of a carry from either adder during the fourth bit time indicates the need for a radix correction from binary to decimal in which case the output of the second adder is selected. Several shift registers, one associated with each word, are provided to store the interdigital carries associated with that word during the processing of other words through the system.

Addition circuit for the digital codes generated in accordance with a nonlinear compression law

Abstract: There is disclosed an arrangement including a translator to derive two linear code signals from two compressed code signals and compressing the resultant sum of the two linear code signals in the translator after addition in an adder circuit. The translator comprises a shift register operating in two directions and a counter.

A Digital System of Simultaneous Addition of Several Binary Numbers

Abstract: —This note is concerned with the design and the function of an electronic digital system of simultaneous addition of several binary numbers, using an arithmetic procedure based on mathematical recurrence formulas established by L. Ponticopoulos.1This electronic digital system presents advantages, compared to the known electronic digital arrangements of series and parallel addition. It is much faster as the set of numbers becomes larger. Also, in all cases, the adder presents simplicity of circuits.

Electronic device for automatic differential diagnosis

Abstract: 1,107,826. Electric selective signalling. NAUTSHNO - TECHNITSHESKA LABORATORIA ZA MEDIZINSKA APARATURA PRI M.N.Z.S.G. 25 June, 1965 [29 June, 1964], No. 27164/65. Heading G4H. Row lines in a matrix are connected with column lines at at least some cross-points by means of a diode in series with a weighted resistor. To diagnose diseases, rows of the matrix, corresponding to diseases, are scanned in turn, to deliver currents to matrix columns corresponding to symptoms, via diode-weightedresistor combinations at some matrix crosspoints. The resistor weight is inversely proportional to the specificity of the corresponding symptom to the corresponding disease. Keyboard switches, closed according to the symptoms present, pass some of the column currents to an adder consisting of an ammeter or operational amplifier. When the adder output exceeds a preset value, scanning is stopped to allow the disease identity to be read on an indicator associated with the scanner. As scanning takes place, the sensitivity of the adder is adjusted by the connection of appropriate shunting resistors. The symptoms not entered on the keyboard but relevant to a particular disease are indicated optically as that disease is scanned, so by not operating any keys all symptoms relevant to each disease in turn are indicated. The invention may also be used for fault or organism identification.

Credit-accumulating arrangement

Abstract: Addition of credits and subtraction of debits is electronically achieved by utilizing an accumulator circuit having multiple stages, each of which includes a binary full adder with a delay flip-flop in a feedback loop.

Arrangements for filtering signals

Abstract: 1,111,863 Ripple suppression ENGLISH ELECTRIC CO Ltd 4 Aug, 1966 [7 Aug, 1965], No 33926/65 Heading H2F A signal is filtered by selecting the unwanted portion in a filter 26, 27, 28, inverting it in transistor 22, limiting the inverted signal by diodes 31, 32 and adding it to the original signal in an adder 20, 30

Improvements in or relating to systems for controlling electrical power

Abstract: 1,135,269 Digital electric calculating apparatus; selective signalling ROSEMOUNT ENG CO Ltd 19 July, 1967 [20 July, 1966], No 32645/66 Headings G4A and G4H [Also in Divisions G3 and H2] An automatic controller includes an arrangement of gates 24-28, Fig 1, opened in accordance with the controlling variable which is presented in pure binary form (modifications to include binary-coded decimal are discussed), the gates also receiving pulse trains derived from the stages of a binary counter 16 fed by clockpulses at 100 c/s derived from the main supply, whereby the merged output pulse train from the gates has an average frequency corresponding to the magnitude of the controlling variable These pulses control a full-wave rectifier 12 which, in turn, controls the power in a load 10 Integral and derivative control can be added to the proportional control by also applying to the rectifier 12 pulses whose average frequency represents the integral with respect to time of the magnitude of the controlling variable, this integral being obtained by counting the pulses produced by the gates 24-28, and pulses whose average frequency represents the rate of change of the controlling variable An arrangement providing proportional and integral control, in which the controlling variable includes a sign bit, is shown in Fig 2 Gates 48-51 are controlled by the magnitude of the controlling variable, and gate 46 is controlled, via an inverter 45, by the sign bit For negative values the sign bit is " 1 " and is negatively weighted, and the magnitude bits are replaced by their ones complement The output pulses from the gates on leads 76 and 77, which are respectively, negatively and positively weighted, represent the proportional control component and are combined in an adder 78 before passing to the rectifier 12 These pulses (76, 77) also pass to a reversible counter 52 whose output will thus represent the integral with respect to time of the controlling input variable The output of the integrating counter 52 is converted, by gates 65-69 into a pulse train 75 having a corresponding average frequency which is also passed to the adder 78 to be combined with the proportional control pulses before controlling the rectifier 12 A suitable arrangement for the adder 78, designed to ensure that no pulses are lost, is described (Fig 3, not shown) In a further embodiment (Fig 4, not shown) derivative control is added to the proportional control

Algebraic theory of flip-flop sequence generators

Abstract: The problem of constructing linear shift registers with a minimum number of adders has provoked interesting research on the theory of trinomials over the field with two elements. Each adder which can be eliminated significantly increases the speed at which the sequence can be generated, and linear shift registers corresponding to trinomials have only one adder. In this paper we describe a class of sequence generators employing J\2-K flip-flops in place of the usual delay elements, and which require no adders or additional gating. J\2-K flip-flops operate at a speed comparable to that of delay elements. If n is the number of flip-flops, then for n = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 15, 17, and 18 a sequence of period 2{su n } \3- 1 can be generated. This sequence is linear and has the well-known randomness and correlation properties. A table in the final section of this paper gives the periodic structure for all n ≦ 19.

Pythagoreas adder or solid state resolver

Abstract: A system for providing the square root of the sum of the squares of two input signals which can also be used to extract the common carrier component of the sin and cos output windings of a synchro differential resolver. Each input signal is applied to a divider means and to a multiplier means. The output of the divider means constitutes the other input to the multiplier means, and the output of both multiplier means are fed to an adder. The output of the adder constitutes the other input to the divider means. In addition, the output of the adder constitutes the square root of the sum of the squares of the two input signals or the common carrier component of the sin and cos output windings of a synchro differential resolver - depending on the application.

Fast Carry-Propagation Iterative Networks

Abstract: —The operation speed of a one-dimensional, unilateral, iterative switching network with strictly combinational cells is often drastically limited by the propagation delays of carry variables. In this paper an attempt is made to extend to other iterative networks the scheme of a fast carry-propagation circuit proposed by several authors for parallel adder. The class of the networks which are realizable according to this scheme is small but contains many networks of practical interest.

Control method and apparatus for extremalizing the value of a final controlled variable of an installation

Abstract: The invention provides an improvement to an usual method of optimalizing the control of an industrial installation by periodically and continuously disturbing a regulating variable governing the operation of the installation. To avoid the drawbacks due to the inherent phase-shift of the installation, the improvement consists in modifying the periodic disturbance in dependence on the instantaneous value of the final controlled variable by multiplying the pilot signal used in the usual control method by a periodic signal having the same shape and frequency as that used in this usual control method, but which is in quadrature therewith, by producing an adapting signal equal to the integral of the result of this multiplication, by adding this adapting signal to a reference signal and by causing the frequency of the periodic disturbance to vary proportionately with the signal resulting from this addition. The apparatus for carrying out this improved method comprises, in addition to the usual circuits, a multiplier, an integrator and an adder connected in succession, the output of the adder being connected to the frequency control input of the generator delivering the disturbance signal.