Showing papers on "Adder published in 1973"

Parallel Counters

Abstract: Multiple-input circuits that count the number of their inputs that are in a given state (normally logic ONE) are called parallel counters. In this paper three separate types of counters are described, analyzed, and compared. The first counter consists of a network of full adders. The second counter uses a combination of full adders and fast adders (that may be realized with READ-ONLY memories), while the third type of counter uses quasi-digital (i.e., analog current summing) techniques to generate an analog signal proportional to the count which is then digitized.

Circuit arrangement for generating pseudo random numbers

Abstract: A circuit for generating pseudo random numbers includes an adder stage having a multiplier connected for serial bit multiple addition. The adder stage is controlled by a sequence switch. The adder stage includes a first register connected to receive a preceding random number, a second register having a constant number, means connected for the serial addition of the outputs of the first and second registers, and a sum register connected to receive the results of the multiple addition. The output of the sum register is connected to the input of the first register under control of the sequence switch. An additional register may be provided, in addition to serial subtractor means for combining the outputs of the sum register and the additional register.

Electronic digital adder having a high speed carry propagation line

Abstract: A parallel, binary adder has extremely high speed carry propagation capabilities. The sum and the carry generated in each stage are developed simultaneously and share much of the same circuitry. In a preferred embodiment utilizing metal oxide semiconductor field-effect transistors, a carry propagation line is charged prior to the addition and carry generation and then is simply discharged or not discharged, depending on the outcome of the computation. In four of the eight possible combinations of inputs to generate a carry-out signal, a carry-in gate is activated, providing a path with no other logic gates and permitting a high speed ripple of the carry signal.

Driving apparatus for display element

Abstract: A driving apparatus for a display element comprises a plurality of sources for generating pulse-width modulated pulse signals each having a different amplitude depending on its source, an adder for adding the pulse signals from the sources together and a discharge tube to which the output of the adder is applied.

Method and apparatus for signal spectrum analysis by hadamard transform

Abstract: A method and apparatus for transforming the analog waveform of a signal into its Hadamard characterization by performing a matrix multiplication using the Hadamard matrix and for analyzing the resulting Hadamard characterization of the signal for identification purposes. A parallel adder system employing recirculating shift registers utilizes the unique properties of the Hadamard matrix so as to reduce the matrix multiplication required in the transformation to a minimal number of simple addition and subtraction operations.

Some New Results on Average Worst Case Carry

Abstract: The previous bound on average worst case carry in a two's complement adder found by Burks et al. [1] is tightened, a bound is established for one's complement adders, and exact expressions for average worst case carry are derived and "experimentally" tested. It is found that an n-bit ripple-carry two's complement adder with carry-completion detection is potentially as fast, on the average, as the old bound indicated an n/√2-bit adder of the same kind would be.

Random error correcting system

Abstract: A rate one half random error correcting convolutional coding system capable of correctng two out of any twelve information and parity bits having an encoder comprising a six stage shift register and a modulo 2 adder connected to the shift register for combining the first, fourth, fifth and sixth information bits present in the register to generate parity bits which are subsequently interleaved with the information bits. A decoder employing another six stage shift register generates syndrom bits by combining parity bits generated from the received information with the received parity bits. The syndrome bits are applied to a six stage syndrome register which is coupled, both directly and via other modulo 2 adder, to a majority logic circuit which provides a correcting signal when the number of ones applied thereto exceeds a predetermined number.

Method and circuit for calculating the square root of the sum of two squares

Abstract: An arithmetic logic circuit for performing an algorithm which approximates the square root of the sum of two squares. A novel hardware arrangement and method are disclosed which employ EXCLUSIVE OR circuits instead of a conventional 2''s complement arrangement provided by conventional adder-subtractor circuits. The values to be squared are converted to positive value digital signals, compared, and the control signal from a comparison circuit used to command the full value of the larger digital signal and half the value of the smaller digital signal into an adder circuit which receives a correction signal in the event either of the input digital values is negative. The correction signal may be added to the least significant order of the adder output signal or to the next to least significant order depending upon whether the larger or smaller of the digital signals is negative.

Voltage controlled oscillator

Abstract: A voltage controlled oscillator comprising an amplifier, a series resonance circuit, formed of a coil, a capacitor and a resistor, to which the output of said amplifier is supplied, a composite circuit for taking the vectorial sum and difference between a voltage across said resistor and a voltage across said coil or capacitor, a circuit for vectorially adding the sum signal and the difference signal at rates responsive to an external control voltage, and means to positively feedback the output of the adder circuit to the input side of said amplifier, the phase of said output of said adder circuit being changed in response to said external control voltage, to make the oscillation frequency of said oscillator variable.

Arrangement for controlling the orientation of characters on a display device utilizing angle defining data syllables and data addition for such syllables

Abstract: An arrangement for illustrating characters which consist of character segments in which data is fed in in the form of code words by means of a character input device, such as a keyboard or a computer. A read only memory stores the character segment data for retrieval and display on a data display device via digital/analog converters and a deflection unit which causes deflection of a character creating element, such as an electron beam, in accordance with the character segment data. An adder is connected to the read only memory and is fed syllables of the character segment data corresponding to angles by which the character to be illustrated is to be disposed with respect to a coordinate system or with respect to a character segment. The adder feeds the digital/analog converters by way of register and decoding apparatus.

MultiFunction Threshold Gates

Abstract: Threshold logic gates, up to now, generally have been presumed to provide a single function of the input variables. The threshold gates that have been integrated [1]-4] were naturally double-sided and provided complementary outputs or, more specifically, complemented dual outputs. This paper shows that the inphase and out-of-phase outputs can, in fact, be designed to provide grossly different functions of the input variables. Two examples of this technique have already been shown [5] and one of these, the full adder, has been demonstrated in a multiplier [6]. Now this technique is generalized, and furthermore, it is shown how each side can be subdivided to provide a number of functions simultaneously. Finally, virtual oRing of specific output points from each side will result in still more functions. The sum-resistor specification for any order function on either side is given. Practical application of these techniques are discussed, including those basic ones that have already been disclosed.

Speed control system for low speed brushless d-c motors

Abstract: The voltages induced in the motor windings of a permanent magnet d-c motor, preferably an axial air gap motor are sensed, halfwave rectified and added in an adder circuit which is connected so that at least a portion of the instantaneous rectified voltages as added, and used as a speed control signal for a speed regulator. The adder circuit may be adjusted in such a way that control signals of double the frequency of modulation with respect to the induced voltages derived from the motor windings at the then instantaneous motor speed are obtained, so that such low speeds as, for example, 33-1/3 rpm, for direct drive of phonograph turntables can be accurately controlled, especially if a motor having a higher number of poles, e.g. 8 poles, is used.

Apparatus and method for serial-parallel binary multiplication

Abstract: The bits of the multiplier are multiplied by sequential bits of the multiplicand in ascending order of significance. These sequential products are supplied to a parallel adder, where each bit is added to the delayed sum of the preceding operation of the next higher bit in order of significance, including the carry bit as the most significant. After k bits of multiplicand have been used, truncated or rounded output becomes available at the output of the least significant stage of the adder. During the bit interval of the last bit of the multiplicand the outputs of the adder are loaded into a parallel input series output shift register, after which the remaining bits of the product are taken from the output of the shift register, the delayed flipflops associated with the adder are cleared and the adder begins to operate on the next multiplication while the shift register is unloading.

Command pulse generator for computer-controlled machining

Abstract: A system has been provided for generating travel command pulses in a machine tool positioning system under computer control which reduces computer computation time and at the same time allows increased machine tool travel speed. Pulse motors driven by pulse trains generated by the system under computer control provide the means for axis movement of the tool. The pulse trains for the axes movements are generated by an addition technique in a hardware hydrid digital differential analyzer. A 24-bit word representing the distance to be traveled along an axis is loaded from the computer core memory into a 24-bit distance register along with an 11-bit word loaded into a 11-bit clock store register which defines the amount of time allowed for tool travel corresponding to the given distance value. Addition is performed serially for each axis in parallel by corresponding 2-bit binary full adders having one input from the particular 24-bit distance register and another input from a 24-bit sum register which is initially cleared. The clock store register, after being loaded by the computer, loads the value into a counter which is counted to an overflow condition. This generates a train of 24 pulses which shift the contents of the distance register and the sum register into the binary full adder. The sum at the adder output is serially loaded into the sum register and repeatedly added to the original distance value, circulated in the distance register, at a rate determined by the rate of application of the train of 24 pulses applied to shift the contents of the distance and sum registers into the adder. A command pulse is generated each time the 24th pulse of a pulse train is generated provided there is an enable due to an overflow in the adder. The time interval between each 24-bit serial addition is determined by the value stored in the clock store register. The addition process is complete for a specific block when a marker bit is in the leftmost bit position followed by all zeros in the sum register. This system requires considerably fewer electronic components and less complicated circuitry to achieve the generation of command pulses at a faster rate while reducing computer time.

Fm demodulation system providing noise reduction property

Abstract: An FM demodulation system having means for noise reduction. The system has a signal path which includes a limiter, an FM demodulation circuit and a gate circuit, and a control circuit which includes a differentiator, two mono-stable-multivibrators, an adder and a gate signal generator. The input of this control circuit is coupled to the output of the limiter and the output of the control circuit is coupled to the control terminal of the gate circuit so as to apply a gate signal to the gate circuit. The gate circuit in the signal path operates in such a way that a demodulated signal is passed to the output terminal of the system when the gate signal is not present and the demodulated signal is prevented from passing to the output terminal when the gate signal is present. The control circuit generates the gate signal when a dropout in the FM signal occurs in the following manner. The signal from the limiter is differentiated by the differentiator and is formed into a narrow pulse train having positive and negative polarities. The positive spikes and the negative spikes of this pulse train trigger the respective ones of two mono-stable-multivibrators, and the outputs from these multivibrators are added by the adder. The output pulse-width of these multivibrator is controlled so that a marker signal appears at the output of the adder when carrier dropout in the FM signal occurs. The gate signal generator generates the gate signal from the marker signal and the resulting gate signal is fed to the control terminal of the gate circuit. a result, a noise component does not appear at the output terminal.

Digital divider circuit

Abstract: The frequency of an input pulse train serves as the dividend and operates a first counter in continuously repeated cycles. The divisor is stored as a binary number in a divisor register and, by means of an adder, the divisor and successive integral multiples thereof are successively registered in a summing register at intervals determined by the operation of a comparator which compares the more significant digits of the summing register with all of the lower integral multiple of the divisor, the adder or the summing register is advanced to present the next higher multiple. The succession of output pulses of the comparator provide a pulse train the frequency of which is the quotient. The divisor may be generated by a pulse train and periodically registered, either as a number proportional to the period of the pulse train or a number proportional to the frequency of the pulse train. The divisor register, adder and summing register have additional places for less significant bits in excess of the number of places in the first counter, enabling great reduction in the maximum rounding error.

Amplitude-to-phase conversion circuit

Abstract: A circuit for converting the angular position of the shaft of a resolver into a phase shift of a carrier wave. Such a conversion circuit may be used for generating a binary number representative of the angle of the resolver shaft. The circuit of the invention requires only a single reactive impedance element which is common to the two adders of the circuit. One of the adders generates a first carrier wave having its phase shifted in one sense while the second adder generates a second carrier wave having its phase shifted in the opposite sense whereby the phase shifts correspond to the angle of the input shaft. Errors due to drift of the components of the network interconnecting the resolver with the adders are minimized because only a single reactive impedance element is used which is common to the two adders. Accordingly, the errors due to drift of the reactive impedance element are reduced by at least one order of magnitude over those of known circuits.

Acoustic direction determination system

Abstract: The disclosure describes a digital acoustic direction determination system comprising a plurality of transducers each capable of producing electrical signals in response to an acoustic wave. Selection logic circuitry determines the octant or 45 degree arc segment from which the sound originates and transmits an octant digital number representing the octant to an adder. As soon as the wave strikes one of the transducers, a clock generator begins to step a shift register which has stored in it a predetermined bit pattern. The sum of the pulses shifted out of the shift register is proportional to the angle within the selected octant from which the sound originates. These pulses are summed in a counter. The contents of the counter are summed in the adder with the digital number representing the octant. The resultant sum is the exact bearing of the sound origin in degrees.

Full adder and subtractor circuit

Abstract: A full adder and subtractor circuit comprises four logic units, wherein a first logic unit carries out a logic operation on first and second operands and on information of a preceding bit to provide an output of carry information; a second logic unit carries out a logic operation on said first and second operands, said information of the preceding bit and said output of the carry information providing a result of an arithmatic operation on the first and second operands; a third logic unit carries out a logic operation on the second operand, the output of the carry information and the information of the preceding bit providing an output of a borrow information, and a fourth logic unit carries out a logic operation on an operation instruction, the output of the carry information and said output of the borrow information providing information of a succeeding bit.

Precharged digital adder and carry circuit

Abstract: Disclosed is a calculator system featuring a precharged carry propagate arithmetic logic circuit. A plurality of data registers store in parallel a plurality of multi-bit data words and are coupled in parallel to the arithmetic logic circuit for executing arithmetic and logic operations thereon. The arithmetic logic circuit is responsive to instruction words for executing either an addition or a subtraction function. A carry propagate circuit is provided for precharging a carry terminal of each bit in the ALU to a reference potential along with a circuit associated with each bit for selectively discharging the carry terminal responsive to the logic level of the previous carry signal into each bit and is further responsive to the appropriate bits of the data words. An exclusive-or adder circuit has an adder terminal precharged to a reference potential during one phase of a clock signal, and further has a discharge circuit for selectively discharging the terminal in response to logic levels of the appropriate bits of the data word and responsive to the carry signal.

Application of Gunn effect to subnanosecond full adder and full subtractor

Abstract: An n-bit parallel full adder and a full subtractor employing Gnnn-effect devices are proposed. The important feature is a high-speed carry generator utilizing transverse spreading of high field domains, whose operation is confirmed by computer study. The delay time of these circuits will be reduced to several hundred picoseconds.

Electro-mechanical actuator

Abstract: A device responsive to electrical control signals for influencing the operation of sewing machine stitch forming instrumentalities to produce predetermined stitch patterns. The device includes a whippletree adder mechanism of which the input arms are selectively influenced by solenoids responsive to the electrical control signals. A mechanical drive is provided from the sewing machine actuating mechanism effective during each stitch for shifting each input arm of the whippletree adder into fully actuated position, in which position the solenoids are selectively energized.

Minimum switching network for generating the weight of a binary vector

Abstract: Vector is divided into three variable sections, and each section is processed by unary-to-binary decoder or adder. Resulting network performs on iterative collection process; all outputs of same kind are collected in same manner. In combination with simple comparator gates, weighting network can also be used as majority network.

High-speed adder and subtractor using Gunn devices

Abstract: This paper will describe a computer study of two-dimensional domain behavior for the design of new high-speed carry generators. Using these devices, the computation time of 30-40 bit full adder and subtractor can be reduced to less than 1 ns.

Integrated adder drive assembly including damper, hydraulic power supply, and paper tape feed

Abstract: A digital hydraulic system converts binary digital input information into displacement of a digital drive. An air reader is used to operate binary latch valves through an air hydraulic interface. A flow sensing system and a hydraulic logic unit cooperate to provide high speed exchange between the piston adders of the digital drive prior to displacement of the load. A hydraulic cylinder sweeps the load about a vertical axis. A self-cooling, air-driven hydraulic pump with an accumulator, provides relatively constant pressure. A damper secured to the piston adders has an additional drive for providing precise location at the end of damping. An incremental paper tape feed with a four motion rack with toggle action indexes the air reader.

A Cellular Array for Binary to BCD Conversion

Abstract: A repeated application of nested multiplication by ten yields an extremely simple method for binary to binary-coded decimal (BCD) conversion where the input is a binary fraction. This technique can be implemented in a cellular array or in a serial system using an adder and storage register. The cellular array is, however, a faster method and can be implemented with available circuits.

Frequency step generator

Abstract: The invention disclosed herein provides a frequency generator having a pair of oscillators producing two frequencies coupled thru individual gate circuits to provide an output of one or another of said frequencies. There is provided a gating circuit and an adder which combines the output frequencies which actuate a Schmidt trigger which in turn actuates a bistable multivibrator which controls the individual gates.