Showing papers on "AND gate published in 1977"

High density N-channel silicon gate read only memory

Abstract: An N-channel silicon gate read only memory or ROM array of very high bit density is made by providing columns in the form of parallel N+ moats separated by field oxide and removing small areas of the field oxide in a pattern of "1's" and "0's" according to the ROM program. Gate oxide is grown in the areas where field oxide is removed, and parallel polycrystalline silicon strips are laid down over the field oxide and gate oxide areas normal to the moats, providing the rows. The ROM may be made as part of a standard double level poly, N-channel, self-aligned silicon gate process. The columns may include an output line and several intermediate lines for each ground line so that a virtual ground format is provided. An implant step may be used to avoid the effects of exposed gate oxide so that zero-overlap design rules are permitted.

Inverters and logic gates employing inverters

Abstract: A so-called "programmable inverter" provides either a direct or an inverse signal path between its input and its output depending on a previously applied programming signal which is arranged to cause selective fusing of a fusible link. Such a circuit element may be incorporated in an input or an output of a logic gate so that a single type of gate may be programmed to perform a selected function from a number of functions.

Two-part current injection interferometer amplifiers and logic circuits

Abstract: Josephson junction interferometers having nonlinear switching or threshold characteristics are disclosed. The nonlinear threshold characteristic is achieved in a preferred manner by applying an injection current to the interferometer at a point on the interferometer which is different from where its gate current is normally applied. The resulting nonlinearity provides for high amplification. The nonlinear switching characteristic may also be achieved by applying an injection current to the same point on the interferometer where the gate current is normally applied. However, a portion of the thus-applied injection current is electromagnetically coupled to the interferometer inductance to achieve the desired nonlinear switching characteristic. Parameters such as the injection current, the gate current, physical point of application of the injection current to the interferometer, junction currents and the inductance of the interferometer may be changed to tailor the threshold characteristic to provide a desired nonlinearity. Logic circuits such as AND, OR and INHIBIT circuits in addition to the basic amplifier circuit are also disclosed.

Schottky-gate field-effect transistor and fabrication process therefor

Abstract: The specification describes a Schottky-gate field-effect transistor and related fabrication process wherein thin ion implanted surface stabilization regions are formed between source and gate electrodes and gate and drain electrodes of the device and to a thickness of between 100 and 1,000 angstroms. This is accomplished utilizing the source, gate and drain electrodes as an ion implantation mask against impinging inert ions which render the implanted regions semi-insulating, and this process requires no post-implantation annealing.

Bistable element and a switch circuit comprising such a bistable element

Abstract: A bistable device comprises a thyristor having anode, cathode and gate electrodes and a transistor having emitter, collector and base electrodes, the emitter-collector path of the transistor being connected to the anode-cathode path of the thyristor. A first control input is connected to the gate of the thyristor for determining one stable state of the device and a second control input is connected to the base electrode of the transistor for determining the other stable state of the device. The first control input is connected through an amplifier to the gate of the transistor.

Split programmable logic array

Abstract: A mask programmable logic array (PLA) for producing a particular digital output given a certain digital input. The input signals to the PLA first pass through a series of AND gates resulting in a predetermined number of product terms being formed. The product signals then pass through a set of OR gates to become the final output signals. In the subject invention, the AND gates and OR gates are implemented through the use of NOR-NOR logic. A first set of NOR gates is implemented in an array to receive input signals and to produce product terms. A second and third set of NOR gates form two arrays. These two arrays are then located on either side of the first array to receive selected product signals in order to produce final output signals. In effect the OR portion of the PLA has been split into two arrays. TABLE OF CONTENTS Subject Background of the Invention Summary of the Invention Brief Description of the Drawings Detailed Description of the Preferred Embodiment The System Block Diagram Microprocessor Unit Pin Designations Clock and Timing Signals System Timing The ROM The Stack Area The RAM Area Elimination of Race Conditions in the RAM The ALU and Control Time Slot End Predictor The CROM Bit Manipulation Scheme Data Pad Input/Output Precharged Data Line Driver Bus Control Test Circuitry Split PLA Control The S-Counter Details of Logic Blocks The MOS/LSI Chip The Chip Test Functions The Instruction Set

Integrated circuit controller programmable with unidirectional-logic instructions representative of sequential wire nodes and circuit elements of a ladder diagram

Abstract: A programmable controller that is programmed to simulate a ladder diagram and accepts input signals to control output devices in accordance with the ladder diagram program and comprising, in addition to a main memory that stores the program, a logic processor and input/output circuits, of a special wire number memory and a control coil memory for receiving, storing and making available to the processor the result of every logic function representing the current on-off status of each wire node and each control coil and associated contacts. This controller affords the maintenance of a complete current record of the changing status of the contacts and their interconnecting circuit nodes. This makes possible a particularly simple unidirectional-logic programming mode because the programmer does not have to keep track of which logic operations must be temporarily stored. This storage affords a powerful monitoring means in that signal tracing can be accomplished by merely calling up predetermined wire numbers from the special wire number memory and displaying the status thereof, or calling up predetermined input devices or control coils to view the status thereof. Moreover, for maintenance purposes, this architecture provides a selector switch and logic circuitry whereby a predetermined wire node may be manually forced "on" or "off" for maintenance purposes or the like.

Computer model and charge transport studies in short gate charge-coupled devices

Abstract: A computer model has been developed that simulates charge transport of carriers in a surface channel charge-coupled device This model is based on the charge continuity and current transport equations with a time dependent surface field The device structure of the model includes a source diffusion an input gate and transfer gate The present model is the first real simulation of the input scheme of the surface-channel CCDs The scooping and spilling techniques associated with the charge injection process are simulated by the input diffusion which is included in the model As an application to a CCD practical problem the present model has been used to study the linearity of the electrical charge injection into surface channel charge-coupled devices The generated harmonic components of a sinusoidal input are calculated using the transfer characteristics of the input stage obtained from the computer simulation Using this model the spatial variations of the self-induced fringing field and total currents under the storage and transfer gates were computed The charge transfer mechanisms for short-gate ( L ≤ 8 μ m) CCDs was investigated It was found that for short gates the charge transfer efficiency is governed mainly by the fringing field and self-induced current mechanisms The results of this study help to clarify the mechanism by which the signal-charge level and gate length affect the charge transfer efficiency

Gate controlled semiconductor device

Abstract: A gate controlled semiconductor device in which a gate electrode is substantially divided into many pieces. The semiconductor device comprises a semiconductive element having at least one P-N junction formed by at least a pair of P-type diffusion regions and N-type diffusion regions, a plurality of cathode assemblies including a metallic layer deposited on a cathode-emitter layer formed on a surface of said semiconductive element, an anode electrode assembly and gate electrode assemblies. The latter includes a plurality of separated metallic layers provided around the cathode electrode assemblies of the cathode-emitter layer. The cathode electrode assemblies are of a radial and spiral shape and the divided gate electrode assemblies have also a ring shape and/or circular shape.

Optical logic elements

Abstract: An improved optical element is provided by an arrangement of optical wavedes disposed with two photoconductive paths and a plurality of electrodes arranged to impress an electric field across the optical waveguide configuration and the photoconductive paths. Optical energy is fed into an input optical waveguide and, dependent upon the optical inputs to the first and second photoconductive paths, an output is produced by the optical waveguide configuration in the manner of a logic gate. Variant configuration of the optical waveguide assembly can be made to perform in the manner of an AND gate, and OR gate, an exclusive OR gate, a NOR gate, or a NAND gate; alternatively, combination configurations can simultaneously perform multiple logic functions.

Arithmetic logic apparatus

Abstract: A system includes arithmetic logic units, each including two 2:1 multiplexers, one 8:1 multiplexer, and a three input majority gate. Each 2:1 multiplexer provides a specific one of two data inputs when a select input signal is at a specific one of two binary states. The 8:1 multiplexer provides output signals indicative of specific ones of eight data inputs in accordance with the binary states of three select input signals. Electrical signals indicative of two input variables are coupled, respectively, to the select input of the two 2:1 multiplexers. Two outputs therefrom are coupled to two of three select inputs of the 8:1 multiplexer, and to two inputs of the majority gate. A carry-in signal is coupled to both the third select input of the 8:1 multiplexer, and to the third input of the majority gate. The arithmetic logic unit acts as an adder, subtractor, AND gate, OR circuit, exclusive OR circuit, and NOR circuit. Arithmetic and logical functions on two input binary variables of the form A0, A1. . .An and B0, B1. . .Bn are performed by an arithmetic logic system comprising n+1 arithmetic logic units. The output of the majority gate of one logic unit is coupled to the carry-in signal receiving means for following logic unit. With appropriate control signals, the system acts as an adder by providing a sum function at the respective outputs of the 8:1 multiplexer, and provides a carry-out function at the output of the (n+1)st logic unit majority gate.

Push-pull switching circuit with minority carrier storage delay

Abstract: A push-pull switching circuit including two grounded emitter transistors 5, 6 controlled by a pair of AND gates 3, 4. The collector output of each transistor is fed back to an input of the AND gate controlling the other transistor, the remaining AND gate inputs being supplied by the Q and Q outputs of a flip-flop circuit 2. During the prolonged conduction of each transistor due to minority carrier storage, its lowered collector potential prevents the enabled AND gate for the other transistor from raising its output and initiating conduction, thereby avoiding overlapping or simultaneous transistor conduction.

Logic gate for cross-tie wall memory system incorporating isotropic data tracks

Abstract: A plurality of data tracks, each formed of a strip of isotropic magnetic film, i.e., having substantially zero uniaxial anisotropy, are configured into a cross-tie wall memory system logic gate. The data-track-defining-strip of isotropic magnetic film utilizes its shape, i.e., its edge contour, induced anisotropy, rather than its easy axis magnetic field induced anisotropy, to constrain the cross-tie wall within the planar contour of the film strip. The use of the shape induced anisotropy of an isotropic strip of magnetic film permits the use of nonlinear, i.e., curved, data tracks. Two input and one output data tracks are configured into an AND/OR logic gate to permit the cross-tie wall memory system to perform both memory and logic functions.

Logic circuit with two pairs of cross-coupled nand/nor gates

Abstract: A logic circuit provided with first and second cross-coupled NAND/NOR gates and third and fourth cross-coupled NAND/NOR gates. The second NAND/NOR gate is arranged to have a delay of output variation longer than that of the first NAND/NOR gate. A desired logic input signal is applied to one input of the first NAND/NOR gate. A first clock pulse is applied to the first and second NAND/NOR gates. A second clock pulse of opposite polarity to the first clock is applied to the fourth NAND/NOR gate. The output of the first NAND/NOR gate is coupled with the input of the third NAND/NOR gate.

Electrical string-instrument

Abstract: An electrical string-instrument having a plurality of strings, a support member stretching the strings, electromechanical transducers respectively corresponding to the strings, a plurality of gate means for gating the outputs from the electromechanical transducers or signals based thereon, and gate signal generating means.

Design verification of large scientific computers

Abstract: Large scientific computers containing 2 million gates can be simulated using a combination of block simulation and gate simulation of 450, 00O gates.

Phase difference detector

Abstract: There is provided a pair of flip-flops, each of which is set before appearance of every one of two input signals to be compared. One of the input signals is applied to a reset terminal of the first flip-flop through an inverter, and the other input signal to that of the second flip-flop through another inverter. There is further provided a pair of AND gates. A set output of the first flip-flop is led to one of two input terminals of the first AND gate through a delay element, and a reset output of the second flip-flop is connected to the other input terminal of the first AND gate directly. The set output of the output of the second flip-flop is coupled to one of two input terminals of the second AND gate through another delay element and the reset output of the first flip-flop is connected to the other input terminal second AND gate directly.

Method for production of insulated gate semiconductor integrated circuit device

Abstract: PURPOSE:B-doped Si is used as a gate Si and gate protecting membrane is formed on the gate Si by Si3N4 mask to decrease threthold voltage fluctuation of MOS element.

Central heating pulse control system - includes twin oscillators and counters, with convertor, comparator and gate arrangement

Abstract: A control system for central heating has an oscillator which feeds pulses to a binary counter connected to a digital/analog converter, with its output connected to the non inverting input of a comparator. The inverting input of the comparator is connected to a device which supplies a signal corresponding to the temperature of the heat supply. The output of the comparator is fed to a differencing device followed by a flip flop. This is connected to an AND gate then an OR gate supplying a control signal to the heat supply. Also connected to the flip-flop is a limiting branch with a second oscillator, binary counter, differentiator and a negation member. This is also interconnected via a second negation member with the two gates.

Multi-phase and gate

Abstract: A no-delay, ratioless AND gate compatible with a four-phase, major-minor clocking scheme and a six-phase metal oxide semiconductor (MOS) system. The disclosed AND gate can be implemented by the interconnection of first and second field effect transistors having conduction paths thereof selectively connected between a respective input terminal and the output terminal of the AND gate to precharge and conditionally discharge the output terminal.

Monitoring circuit for battery charge state - has several cells connected in series and uses series chain of transistors to balance cell loads

Abstract: A limit switch (T11-Tn1) is connected in parallel with each cell (B1-Bn) and controlled by the respective cell voltage. Switch outputs are connected to the inputs of a series AND gate (G) which operates a switch (T1) between the battery and load (RL). Threshold value transistors may be used as the limit switches (T11-Tn1). The base terminal of each of the latter is connected through a resistor (R12-RnZ) to a second set of transistors (T12-Tn2) which together form the series AND gate (G) with a coupling transistor (T2). The transistor chain enables the load on each cell to regulate itself in accordance with the state of charge.

Precharged data line driver

Abstract: For use in a microprocessor on a single semiconductor chip, circuitry responsive to a timing signal and a data signal for discharging a precharged data line to correspond to the data to be transmitted on the data line. First and second enhancement-type field effect devices are connected in series with the drain of the first device being connected to the data line and the source of the second device being connected to a source voltage. The gate of one of the field effect devices provides an input for the timing signal. The gate of the remaining field effect device provides an input for the data signal. A depletion-type field effect device has its source and gate coupled to the series connection point and its drain connected to a drain voltage source. The depletion-type field effect device prevents a charge redistribution from the data line to the series field effect devices when these devices are not discharging the line.

Simplified control electronics for a practical cycloconverter

Abstract: Actual control circuitry using simple integrated-circuit components as developed for a practical implementation of a three-phase half-wave thyristor cycloconvertrr are discussed iu some detail. Cosine-wave crossing principle is used for phase control. Except for a few voltage comparators and operational amplifiers, most of the control functions required in the present scheme are realized by using simple Nand logic elements, thus resulting in an overall economy, simplicity and reliability. Circuit operations are discussed for both circulating and non-circulating modes of cyclo-convertor operation. Typical firing and logic circuit waveforms as well as cycloconverter waveforms with R-L and induction motor load as obtained from experimental results are presented to demonstrate the successful operation of the control circuits.

Fail-safe acknowledging circuit

Abstract: A fail-safe solid-state acknowledging circuit for a cab signaling system requiring an acknowledgment after the reception of a more restrictive speed command signal employing a plurality of transistor latching circuits having a predetermined order of more restrictive significance. Each of the transistor latching circuits is coupled to one input of a separate two input OR gate while a separate a.c. transistor amplifier is coupled to the other input of each of the two input OR gates. The outputs of the OR gates along with an acknowledging switch controlled voltage are coupled to the inputs of a multiple input AND gate for normally holding the AND gate in a signal passing condition and for causing the AND gate to assume a signal blocking condition when a more restrictive speed command signal is received onboard a vehicle.

Josephson self gating and circuit and latch circuit

Abstract: A Josephson Self Gating And circuit which is powered by pulsed or clipped alternating current and provides true and complement outputs in response to true and complement inputs is disclosed. Inputs applied during the duration of the applied pulsed power or clipped alternating current are delivered to outputs which are maintained in that state in spite of a change of input within the given pulse duration. In one embodiment, the presence of an output signal interrupts a current path which, in turn, disables a pair of AND gates. These gates, even though the input to them changes, can provide no other output until the applied power falls to zero resetting the pair of AND gates which are latching in character. In another embodiment, current paths of one AND gate are cross-coupled with a current path of another AND gate. The interruption of current in a serially disposed Josephson device in one or the other of the current paths disables one or the other of the pair of AND gates preventing a change in outputs until the next cycle of applied pulsed or alternating current power. A latch circuit incorporating a pair of AND gates, a flip-flop and a Self Gating And circuit is also disclosed. The latch permits an input different from a previously applied input to the flip-flop to change the state of the flip-flop without changing the output of the Self Gating And during the application of a cycle of pulsed or alternating current power. The changed input to the flip-flop appears at the output of the Self Gating And circuit during the next cycle of applied pulsed or alternating current power.

Electronic counter for summing pulsed measurement values - operates with sources giving measurement values in different ranges using clock and address generators with coupled astable flip flops

Abstract: An electronic counter for summing measurement values in the form of electrical pulses from two or more sources is designed to operate with sources giving values in different ranges. Each source is associated with a pulse register bistable flip flop with bistable preset counters whose outputs are connected to several AND gates controlling an astable flip flop. A clock generator and address generator are made with coupled astable flip flops. Each pulse register is connected to one input of an associated three input AND gate whose other two inputs are connected to the address and clock pulse generators. Each AND gate output is connected to a multiplier circuit and, via an OR gate, to a common divider circuit. Each multiplier output is connected to the corresponding pulse register reset channel.

Input*output control system

Abstract: PURPOSE:To reduce the instruction start time of input/output control device, by scanning and referring the inquiry memory before the end of operation of I/O is informed to CPU, and providing the means to store the content when inquiry is made CONSTITUTION:A scanning circuit II12 is started with a machine cycle and signal, and the input of a multiplexer MPX3, ie, the scanning of the content of an inquiry memory 1 is made before the information of CPU As a result, if at least one inquiry state is present in the memory 1, FF15 is set and the presence of inquiry is stored Thus, an AND gate 9 is closed and the input and output start instruction is waited After that, FF8 is set with the scanning end signal I of a scanning circuit I11, FF15 is reset with the output Q, the gate 9 is opened, the machine cycle start signal is formed, and the machine cycle start circuit 10 is started If no inquiry is made, FF15 is not set, the output Q of FF8 is 0, the gate 9 is opened, the I/O controller is immediately operated and the instruction start time is reduced

Storage matrix with single transistor memory elements - has FET with U-shaped drain electrode and connections to storage capacitor and bit line

Abstract: The single transistor memory element has a drain (30) source (20) and gate (40) electrodes. The bit line conductor (10) is connected to gate electrode, and the source (20) is a doped region mounted on a silicon substrate of p-type conductivity. The drain electrode has a U-shaped profile and its dimensions are such that in normal operation no electrical connection can be made with the doped source region. Meander-shaped connections are used to form a matrix array out of the single unit elements. An insulating film is provided between gate electrode (40) of the FET and the gate electrode (50) of a storage capacitor. A number of parallel word-lines are provided, each alterante line have a connection to the FET associated with one bit line and the intermediate word-lines associated with the others.

Current mode 4-bit arithmetic logic unit with parity

Abstract: An arithmetic logic unit employing soft-saturating current mode logic gates receives as inputs two 4-bit plus parity bytes and generates a 4-bit plus parity binary output byte in accordance with the particular operational mode prescribed by a binary operation mode control signal. The unit performs sixteen binary arithmetic or sixteen Boolean logic operations on two 4-bit plus parity input fields Ai and Bi. A carry-in input CIN, a carry generate output G, and a carry propogate output P are provided so that the device can be utilized in a full carry look-ahead configuration with a separate carry look-ahead array. A special output F=O is provided for zero detection purposes. In addition to the arithmetic and logic operations, the unit performs parity checking, parity carry, and parity prediction operations on the 4-bit plus parity binary input signals, and accordingly special inputs in the form of a carry-in duplicate CID, parity of the half-sums HS, a parity of the half-parities HP, parity of the carries PC, carry error CE, and parity checking command PCK are provided. A special output E indicates a carry or half-sum parity error. A carry-out signal COUT is also provided. The device can be configured to operate on bytes having fewer than four data bits by means of a pair of configuration select signals P1 and P2.

Insulated gate type field effect transistor and its production

Abstract: PURPOSE:To produce an IG-FET of a short channel length and higher performance by isolating source and drain regions with a notched portion and providing an insulating film and gate electrode along the notched face.