Showing papers on "Asynchronous communication published in 1979"

Access-control disciplines for multi-access communication channels: Reservation and TDMA schemes

Abstract: Reservation and TDMA schemes are studied for governing the access-control discipline for a network of terminals communicating through a multi-access broadcast channel. A single repeater is employed to allow a fully connected network structure. A channel can be characterized as inducing a Iow propagation-delay value, as for terrestrial radio or fine networks, or as being associated with a higher propagation-delay value, as for a satellite communication channel. A synchronized (slotted) communication medium is considered. Messages are composed of a random number of packets, governed by an arbitrary message-length distribution. The process describing the number of reserved message arrivals within each time frame is assumed to be a sequence of i.i.d, random variables, governed by an arbitrary distribution. (A Poisson arrival stream thus becomes a special case.) The reservation access-control disciplines studied in this paper employ message-switching distributed-control procedures. The performance of each access-control scheme is evaluated according to its delay-throughput function. In particular, schemes are developed to adapt their structure, or protocol, dynamically to the underlying fluctuating network traffic-flow values. A fixed-reservation access-control (FRAC) discipline is studied, employing a fixed periodic pattern of reservation and service periods. The reservation periods are used for the transmission of reservation packets as well as for the integrated service of other groups of network stations. The latter stations can access the channel during these periods, using any proper access control procedure. As a special case, message-delay distributions and moments under a TDMA scheme are obtained. Using dynamic estimates of the underlying message traffic parameters, a dynamic fixed-reservation access-control (DFRAC) scheme is obtained. An analytical technique, which employs a Markov ratio limit theorem, is presented for the derivation of the delay-throughput performance curves of dynamic demand-assignment reservation schemes. To illustrate its application, asynchronous reservation demand-assignment (ARDA) schemes are developed to adapt automatically to the underlying network traffic characteristics. Such schemes establish reservation slots dynamically according to observed network service demands and queue sizes.

Some Analysis Techniques for Asynchronous Multiprocessor Algorithms

Abstract: Efficient algorithms for asynchronous multiprocessor systems must achieve a balance between low process communication and high adaptability to variations in process speed. Algorithms that employ problem decomposition may be classified as static (in which decomposition takes place before execution) and dynamic (in which decomposition takes place during execution). Static and dynamic algorithms are particularly suited for low process communication and high adaptability, respectively. For static algorithms the following analysis techniques are presented: finding the probability distribution of execution time, deriving bounds on mean execution time using order statistics, finding asymptotic mean speedup, and using approximations. For dynamic algorithms the technique of modeling using a queueing system is presented. For each technique, an example application to parallel sorting is given.

Data distribution interface

Abstract: A microprocessor-based circuit for interfacing between a plurality of serial data terminals and an external parallel data operating system. The interface circuit includes an asynchronous receiver-transmitter, which converts serial data to parallel data and converts parallel data to serial data. The interface circuit multiplexes received serial data from the terminals and couples that serial data to the receiver-transmitter. The microprocessor in the interface circuit further controls the transfer of this now-parallel data to the external parallel data operating system. The microprocessor also controls the transfer of parallel data from the parallel data operating system, which is converted to serial data by the asynchronous receiver-transmitter, demultiplexed by the interface circuit and transmitted to the terminals. Both the transmission and the reception of serial data is coordinated by the microprocessor, which also controls the receiver-transmitter and a set of registers connected to the operating system on a parallel data bus.

Automatic synchronizing system for digital asynchronous communications

Abstract: An asynchronous system for transmitting digital data from a data origination station to a data utilization station over a communications path such as an ordinary long-distance telephone network is disclosed. The system includes circuitry for synchronizing and maintaining synchronization between the receiving circuits and the transmitting circuits and for correcting errors introduced by the communications path. Each data word transmitted has associated therewith a synchronization code comprising a stop bit and a start bit. During normal operation, the system is synchronized by detecting the start bit which precedes the information portion of each data word. Synchronization is maintained for several data words even though the start bit is not detected due to interference, for example, by an auto-synchronization signal which includes a pulse positioned within the time period during which the start bit would normally be detected. Additionally, should a predetermined number of successive data words arrive at the receiver with errors, the auto-synchronization signal is disabled based on the assumption that the errors are due to a loss of synchronization. The transmitter circuits then transmits two synchronizing words, each containing the synchronization code with all other bits having a logic "zero" level. The synchronization code of the two synchronizing words resynchronizes the system thereby restoring normal operation. That is, the system maintains normal synchronization even though interference destroys the start and/or stop bits of a number of successive words. Should this interference continue such that the automatic synchronization circuits can no longer maintain synchronization, the auto synchronization circuit is disabled and normal synchronization is restored by transmitting two special synchronization words, all without any loss of data.

Shared storage for multiple processor systems

Abstract: A system is provided that includes a plurality of processors connected to a shared storage via an asynchronous storage interface that includes various interface logic and a ring counter that performs polling of the processors for access to the shared storage. The ring utilizes a "lookahead" feature that bypasses stages in the ring to speed up responses to request signals from the processor. The logic uses the clock from the particular processor accessing the shared memory at any point in time.

Data processing system incorporating arbiters and selectors to allocate transmissions by multiple devices on a bus

Abstract: Disclosed is a data processing system which includes a plurality of devices that communicate in a time-shared fashion over a single data bus. The system also includes a network of arbiters and a network of selectors. These networks interconnect the plurality of devices, and they operate to insure that only one device transmits on the bus at a time. The networks are asynchronous and modular in design.

Interleaved TDMA terrestrial interface buffer

Abstract: A common memory is used for asynchronous interleaved read and write operations. TDMA data compression and expansion is performed without ping-pong memories and elastic buffering is also possible. A buffer reset method is used to automatically slip a fixed number of bits in response to excessive phase shift between the read and write clock.

Synthesis of Asynchronous Machines Using Mixed-Operation Mode

Abstract: In this correspondence, we have introduced the concept of mixed-operation mode (MOM) in asynchronous sequential machines.

High speed synchronization circuit

Abstract: In a high speed synchronizing circuit, the rising edge of an asynchronous input signal is used to set an input RS flip-flop. First and second latch registers monitor the input RS flip-flop. Each latch register generates a reset signal before a change in the logic level of the system clock for resetting the input RS flip-flop. The reset pulses are very narrow which enables the RS flip-flop to be quickly conditioned to receive the next asynchronous signal.

Use of memories and programmable logic arrays for asynchronous sequential circuits

Abstract: The design of asynchronous sequential circuits is commonly related to the problem of observing some specific timing constraints to avoid unreliable behaviour. State assignment and hazard-free construction of the combinational circuits for the state transition equations are the most essential topics to investigate. They contribute significantly to the design, particularly in comparison with that of synchronously operated systems. On the other hand, the application of digital circuitry for solving control tasks implies more and more asynchronous interaction between the controller and the controlled unit, and also the use of modern, highly-integrated modules. This paper investigates the possibility of applying arbitrarily chosen, but unique, codes for state assignments, using l.s.i. memories and programmable logic arrays for implementing more complex asynchronous sequential circuits than is possible with discrete or s.s.i/m.s.i. components. A basic model is derived to describe the time properties of such matrix arrays, and design rules are established to decide easily by some simple measurements, if a given module may be used in that application. The results of a broad investigation into available memories and field-programmable logic arrays show that reliable asynchronous sequential circuits may be implemented without having hazard problems and the need for special state-assignment procedures.

Efficient interaction for automated chromosome analysis using asynchronous parallel processes.

Abstract: It is likely that any practical automated chromosome analysis system will be interactive. To prevent long pauses in the stream of operator interactions, it is necessary, if using standard computer hardware, to configure for asynchronous and parallel operation. A system is presented which uses several computer processors, which can support one or more operators, and which divides processing into interactive and noninteractive sections, smoothes the rate of presentation of interactions, and keeps both the operator and the computer fully employed.

Practical applications of path pascal in systems programming

Abstract: This paper presents both a description of a programming language and development system suitable for writing practical asynchronous systems and several examples of its use. Path Pascal is a high level programming language which includes objects for encapsulation, processes which execute independently, pathexpressions for synchronization, and provisions for coding interrupt processes. Path Pascal allows code for synchronization and coordination of asynchronous systems to be written entirely in a high level language and is currently implemented on several computers: the CDC Cyber family, the entire PDP-11 family, the Z80 microprocessor, and the PRIME 500. Path Pascal has been used to construct model operating systems, including software to share several I/O devices and a CPU among a stream of batch Jobs.

Analysis of data flow models using the SARA graph model of behavior

Abstract: A number of investigators have continued to discuss application of asynchronous techniques to improve the computational power of computing systems. 2 , 12 , 5 , 9 In fact the need for asynchronous design techniques arose in the earliest machines 26 , 20 , 6 which introduced parallel handling of bits in a number and overlapping of independent operations. The concept of distributed autonomous concurrent processors was essential to the visionary architecture proposed by Holland 16 to support "operating programs floating in a sea of hardware." The importance of such concurrent and asynchronous systems has increased recently because of the availability of entire processing units on one or a few chips and the potential cost reduction of those units. Moreover, it is expected that work on VLSI technology will permit even more complex systems to be reduced to silicon if their design and market analysis have been validated sufficiently to justify the cost. The need for validation prior to costly physical implementation has increased the value of methods and tools which support modeling and analysis.

Speed-independent asynchronous arbiter

Abstract: A very simple asynchronous arbiter is given for n concurrent asynchronous processors interconnected in a speed-independent way. The arbiter consists of one inverter and n identical modules each incorporating a recently described 2-user arbiter.

Performance of a dataflow computer

Abstract: Author(s): Gostelow, Kim P.; Thomas, Robert E. | Abstract: Our goal is to devise a computer comprising large numbers of cooperating processors (LSI). In doing so we reject the sequential and memory cell semantics of the von Neumann model, and instead adopt the asynchronous and functional semantics of dataflow. We briefly describe the high-level dataflow programming language Id, as well as an initial design for a dataflow machine and the results of detailed, deterministic simulation experiments on a part of that machine. For example, we show that a dataflow machine can automatically unfold the nested loops of n-by-n matrix multiply to reduce its time complexity from O(n^3) to 0(n) so long as sufficient processors and communication capacity is available. Similarly, quicksort executes with average 0(n) time demanding 0(n) processors. Also discussed are the use of processor and communication time complexity analysis and "flow analysis", as aids in understanding the behavior of the machine.

Remote monitor control unit of multiimicroprocessor system

Abstract: PURPOSE:To reduce the load of the main processor, by parallelly connecting a plurality of slave processors taking the communication control functions as exclusive jobs to the common bus of one major processor with the help of the asynchronous first-in and first-out memory. CONSTITUTION:The input 1 to 16 from the monitored stations are converted into digital signal with the FSK demodulation circuit 1, and the photo coupler 3 is driven with the buffer 2. Next, this outpt is fed to the programmable I/O port 4, and latching is made by using the control pulse 19 from the timing generating circuit 8. After that, the processor 5 receiving the interrup signal 18 reads in the data latced in the port 4, and it detects the conditional change information of the input signals of 16 sets according to the program stored in the memory 6. In this case, the slave processors 17,21,22 taking the communication control function as exclusive jobs are provided to the circuit terminal channel by one to 16 channels separately, and data are delivered to the main processor 16 via the asynchronous FIFO memory 7.

A Constructive Solution To The Extensibility Problem In Real-Time Computer Systems

Abstract: Computer technology appears to be reaching a point of diminishing returns in attempts to increase the basic speed of uniprocessor systems. In order to avoid overloading, vfhich may be disastrous in real-time systems, a multiprocessor configuration may be necessary. The configuration should be easily extensible to accommodate system growth. A design methodology is presented which assists in the realization of a real-time computer system as a set of asynchronous cooperating processes. Both hardware and software design principles are applied to achieve parallel processing, processor sharing, and device sharing in an extensible, loosely coupled, multiprocessor configuration. The theme underlying our methodology is that a real-time computer system should be a product of the requirements of its environment, and not vice versa. Furthermore, we have followed the principle that software and hardware are two equally important aspects of computer system design; and, at the architecture level, they should be ...

Improvements in or relating to digital data transmission

Abstract: A data transmission system to enable data to be transmitted along a transmission path at a rate C greater than the upper data rate limit A of the path. A data transmitter driven by an internal clock at C Hertz transmits data along the transmission path and at the same time also transmits a derived clock signal at a frequency C/N Hertz where < A along the path. At the receiver the data is clocked into a series of data stores under the control of the transmitted clock signal and is thereafter recombined into a serial stream under the control of the clock signal driving the receiver.

Signal input circuit to computer

Abstract: PURPOSE:To enable the input of a number of asynchronous serial digital signals, by utilizing the programmable peripheral interface having the latch circuit and the interrupt function to computer and increasing the number of the latch circuits in the permissible range of the processing speed of computer. CONSTITUTION:The circuit is provided with the programmable peripheral interface 17 latching the input signal from the asynchronous serial digital signal lines 1 to 16, and the latched timing signal is fed from the demultiplier 18 demultiplying the reference signal of the microcomputer 19. Further, the input signal is sampled with the timing of 1/(2n+1) (where: n is an integer more than 1) of the nominal delivery speed, and the sampling and the sampling data immediately before it are compared. If there is a change between the logical value of the both data, the n-th data from the sampling time point is judged as true data, if no change, the data at 2n+1-th data from the sampling time point judging immediately before the true data is judged as the data of continuous input signal.

Power source synchronizing timign set up circuit

Abstract: PURPOSE:To easily obtain the time limit synchronized with alternating power source, by using analogue control element, such as variable resistor etc., as the timing set up device of timer circuit for resistance welding machine and forming asynchronous time limit as the power source through a simple synchronous control circuit. CONSTITUTION:Selection of the analogue switch 2 is determined by each bit output condition of the ring counter 3 composed of the shift register and gate circuit at the timer circuit for resistance welding machine and the value of selected timing set up device 1 is taken in the timing set up circuit 4 composed of IC for timer etc. and then, time limit digital signal is formed. Basing on the above signal, the one shot circuit 5 making clock pulse, is connected with clock input of the counter 3 together with starting pulse. Alternating power source voltage is inputted in the pulse conversion circuit 7 through the transformer 6 and the above signal is made as clock signal. Then, the clock signal is connected with the D type flip flop circuit 8 converting welding current charge time limit signal QW to D input signal and the bit output E is synchronized with QW.

Multipleeaddress radio communication system and its receiver

Abstract: PURPOSE:To eliminate the open leakage of important information by allowing the receiver of a system, which transfers information to a specific receiver in a specific area, to receive a general broadcast normally and to receive a multiple-address signal by switching automatically and definitely for multiple address communication. CONSTITUTION:The multiple-address radio talking system including a multiple- address transmitter and multiple-address receiver is equipped with synchronous communication start signal generating part 4 and multiple-address communication object receiver selective signal generating part 5, which are both connected to alternation switch S1 for multiple-address communication mudulation contents generating a pre-signal and multiple-address signal, at radio transmission section 200. Further, specific receiver 200 is provided with medium-wave and FM-wave broadcast reception parts 16 and 17 which receive general midium waves and radio waves from FM broadcasting station 24, and multiple-address communication object listener selective signal discrimination part 13 connected to multiple-address reception part 13 detecting pre-signals generated by generating parts 4 and 5 in transmission section 200, in addition to receiver-content alternation switch S3 and general-broadcast switch S7 controlled by FF23 which changes general-broadcast reception over to multiple-address signal reception.

A Formal Model of Atomicity in Asynchronous Systems

Abstract: We propose a generalisation of occurrence graphs as a formal model of computational structure. The model is used to define the "atomic occurrence" of a program, to characterise "interference freeness" between programs, and to model error recovery in a decentralised system.