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Showing papers on "Automatic test pattern generation published in 1967"


Journal ArticleDOI
Arthur D. Friedman1
TL;DR: It is shown that a set of diagnostic tests designed for a redundant circuit under the single-fault assumption is not necessarily a valid test set if a fault occurrence is preceded by the occurrence of some (undetectable) redundant faults.
Abstract: It is shown that a set of diagnostic tests designed for a redundant circuit under the single-fault assumption is not necessarily a valid test set if a fault occurrence is preceded by the occurrence of some (undetectable) redundant faults. This is an additional reason (besides economy) for trying to eliminate certain kinds of redundancy from the circuit. However, single-fault analysis may remain valid for some types of redundancy which serve a useful purpose, such as the elimination of logic hazards in two-level circuits.

94 citations


Journal ArticleDOI
TL;DR: Methods for generating tests for combinatorial and sequential logic circuits are discussed and an integrated approach that uses many of the existing methods plus new techniques is described and illustrated.
Abstract: Methods for generating tests for combinatorial and sequential logic circuits are discussed. A survey of existing techniques is given. An integrated approach that uses many of the existing methods plus new techniques is described and illustrated.

13 citations


01 May 1967
TL;DR: A preliminary approach for extending the circuit techniques to the system level and results directly related to the problem of fault diagnosis and a significant amount of information is included regarding practical aspects of topological methods of network analysis.
Abstract: : The work under this contract was directed toward the development of improved techniques for diagnosing faults in conventional electronic systems. Detailed procedures for component fault diagnosis of linear and nonlinear circuits are presented. Also included is a preliminary approach for extending the circuit techniques to the system level. These techniques for fault isolation are based on the analysis and measurement of various network transfer functions of the circuit under test. The required test points for these techniques are limited to the normally available input/output terminals, thereby reducing the complexity of required test procedures and equipment. Illustrative examples and experimental results are presented. A FORTRAN-IV computer program developed during the course of this contract is described. The computer program is capable of automatic generation of test specifications and fault diagnosis tables for conventional linear circuits of practical size. The computer program listing has been delivered as a separate item from this report due to its size, approximately 10,000 FORTRAN statements. In addition to the results directly related to the problem of fault diagnosis, a significant amount of information is included regarding practical aspects of topological methods of network analysis. In particular, the computational aspects of tree generation are discussed in detail. (Author)

2 citations