Showing papers on "Barrier layer published in 1995"

Method for depositing a tungsten layer on silicon

Abstract: This invention is a process for depositing tungsten metal on a silicon surface with the deposited layer having improved uniformity of thickness over prior art deposition techniques. The process involves the steps of removing any native silicon dioxide present on the silicon surface, forming a barrier layer which overlies the silicon surface which prevents the upward diffusion of silicon atoms from the polycrystalline surface, and depositing a final tungsten metal layer on top of the barrier layer. The barrier layer is preferably a refractory metal nitride. It may be formed directly by chemical vapor deposition, by reactive sputtering, or it may be formed indirectly by depositing a preliminary tungsten metal layer, subjecting the preliminary layer to a plasma formed from NH3 and N2 gases. Both preliminary and final tungsten metal layers are deposited preferably via chemical vapor deposition using the WF6 and SiH4 as reactants.

A conductive amorphous-nitride barrier layer for high dielectric-constant material electrodes

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), a conductive exotic-nitride barrier layer (e.g. Ti-Al-N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the exotic-nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The exotic-nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.

Glass substrates coated with a stack of thin layers having reflective properties for infrared and/or solar radiation

Abstract: Transparent substrate is coated with a pile of thin layers, with reflective properties in the infrared and/or in the solar radiation domain. A transparent substrate (1), notably of glass, provided with a pile of thin layers incorporates at least one metal layer (4) with properties in the infrared, arranged between an underlying oxide anchoring layer (3) deposited on a first coating of dielectric based material (2) and an upper protective layer (5) surmounted by a second coating of dielectric based material (9). With a view to preventing the modification of the properties of the pile, in the case where the carrier substrate (1) is subjected to a heat treatment of the tempering or bending type, the second dielectric based coating includes at least one oxygen diffusion barrier layer (7) and the functional metal layer is deposited directly on the anchoring layer. Independent claims are also included for: (a) a low emission or antiglare multiple glazing incorporating such substrate; (b) a laminated glazing incorporating such substrate; (c) a method for the fabrication of the substrate; (d) utilization of the substrate in which the substrate is curved, annealed or tempered; (e) an assembly of glazing incorporating the tempered, curved or annealed substrate.

Method of forming conductive amorphous-nitride barrier layer for high-dielectric-constant material electrodes

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. TiN 50), an amorphous nitride barrier layer (e.g. Ti--Si--N 34) overlying the oxidizable layer, an oxygen stable layer (e.g. platinum 36) overlying the amorphous nitride layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlying the oxygen stable layer. The amorphous nitride barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer.

Vessel of plastic having a barrier coating and a method of producing the vessel

Abstract: A plastic vessel has a barrier coating comprising sequentially arranged barrier layers of organic polymer and of inorganic oxides, nitrides or oxynitrides. The barrier coating preferably has at least two inorganic barrier layers. The thickness of the inorganic barrier layers lies between 2 and 300 nm and the thickness of the organic barrier layer lies between 2 and 1000 nm. The total thickness of the layer packet should not exceed 0.1 mm.

Barrier layer cladding around copper interconnect lines

Abstract: In a method for fabricating an integrated circuit interconnect upon a semiconductor substrate an integrated circuit component is formed upon the surface of the semiconductor substrate. A copper interconnect is formed and electrically coupled to the integrated circuit component. A metal is introduced in the copper interconnect to provide an introduced metal. A gas is reacted with the implanted metal to form a barrier layer cladding upon the copper interconnect. The metal is introduced substantially near the surface of the copper interconnect and substantially all of the introduced metal diffuses to the surface and reacts with the gas. Thus the resistivity of the introduced interconnect is substantially equal to the resistivity of copper. The metal can be, for example, titanium, tantalum, chromium, aluminium or tungsten. The gas can contain, for example, nitrogen, oxygen and carbon.

Electrode structure for ferroelectric capacitor integrated on silicon

Abstract: A ferroelectric capacitor structure and its method of making in which a ferroelectric stack of two metal-oxide electrodes sandwiching a ferroelectric layer is fabricated on a silicon substrate with an intervening barrier layer, preferably of TiN. In one embodiment, a platinum layer is grown between the TiN and the lower metal-oxide electrode at a sufficiently high temperature that provides crystallographically ordered growth of the ferroelectric stack. In another embodiment, the platinum layer was completely eliminated with the lower electrode being grown directly on the TiN. Although the conventional conductive metal-oxide used in the electrode is lanthanum strontium cobalt oxide (LSCO), lanthanum nickel oxide provides good electrical and lifetime characteristics in a ferroelectric cell. Alternatively, the electrodes can be formed of the rock-salt metal oxides, such as neodymium oxide (NdO).

Process for fabricating ferroelectric integrated circuit

Abstract: An oversize ferroelectric capacitor is located against the contact hole to the MOSFET source/drain in a DRAM. A barrier layer made of titanium nitride, titanium tungsten, tantalum, titanium, tungsten, molybdenum, chromium, indium tin oxide, tin dioxide, ruthenium oxide, silicon, silicide, or polycide lies between the ferroelectric layer and the source drain. The barrier layer may act as the bottom electrode of the ferroelectric capacitor, or a separate bottom electrode made of platinum may be used. In another embodiment in which the barrier layer forms the bottom electrode, an oxide layer less than 5 nm thick is located between the barrier layer and the ferroelectric layer and the barrier layer is made of silicon, silicide, or polycide. A thin silicide layer forms and ohmic contact between the barrier layer and the source/drain. The capacitor and the barrier layer are patterned in a single mask step. The ends of the capacitor are stepped or tapered. In another embodiment both the bottom and top electrode may be made of silicon, silicide, polycide or a conductive oxide, such as indium tin oxide, tin dioxide, or ruthenium oxide.

Method for producing electroless barrier layer and solder bump on chip

Abstract: The present method for producing a barrier layer and a solder bump on a chip includes: a) providing a silicon chip with a bump base; b) forming a metal pad, e.g. an aluminum pad, on the bump base; c) having the metal pad contact with a solution containing about 120˜150 g/l NaOH, 20˜25 g/l ZnO, 1 g/l NaNO3 and 45˜55 g/l C4 H4 KNaO6 ·4H2 O to form thereon a zinc layer, and preferably further containing tartaric acid for reducing a dissolving rate of the metal pad.; d) having the zinc layer contact with a deposition solution to deposit thereon an electroless barrier layer, e.g. an electroless Ni-P layer; and e) dipping the resulting silicon chip into a molten solder bath to form a solder bump on the electroless barrier layer. The present invention is a simple process for manufacturing an electroless Ni-P and a solder bump on a chip.

Method for fabricating gate oxide layers of different thicknesses

Abstract: A method for fabricating gate oxide layers of different thicknesses on a silicon substrate. A field oxide layer is formed on a predetermined portion of the silicon substrate to define first active regions and second active regions. A first gate oxide layer is formed over the first and second active regions. A barrier layer is formed to cover a portion of the first gate oxide layer within the first active regions. The portion of the first gate oxide layer within the second active regions is then removed utilizing the barrier layer as masking. A second gate oxide layer is then formed over the second active regions.

Semiconductor structures using high-dielectric-constant materials and an adhesion layer

Abstract: A semiconductor device (10) is illustrated, which is formed on an active region (14) of a semiconductor substrate (12). Device (10) comprises a conductive plug (20) and a barrier layer (22) formed in an opening in an interlevel isolation layer (18). An inner electrode (24) is caused to adhere to the interlevel isolation layer (18) through the use of an adhesion layer (26). High-dielectric-constant layer (28) and an outer electrode (30) are formed outwardly from inner electrode (24).

Process for fabricating integrated circuit devices

Abstract: A process for fabricating an integrated circuit device comprises a first step of forming an opening in an insulating layer formed on a substrate, a second step of depositing a copper layer on the substrate including the opening, a third step of abrading the copper layer to remove the copper layer deposited on the insulating layer, while part of the copper layer deposited in the opening is removed until the upper surface of said part becomes lower than the upper surface of the insulating layer, a fourth step of depositing a barrier layer on the substrate including the copper layer in the opening, and a fifth step of abrading the barrier layer to remove part of the barrier layer on the insulating layer while part of the barrier layer on the copper layer in the opening is left, so as to planarize the surface. A wiring layer of copper can be formed without a conventional step of etching a copper layer to leave a wiring layer. Furthermore, the copper wiring layer is coated by layers of barrier materials, whereby oxidation and diffusion of the copper is precluded with a result that planarized wiring layers of high electromigration resistances and low resistances can be formed.

Semiconductor device comprising composite barrier layer

Abstract: A semiconductor device comprising conductors electrically connected through a contact hole interlayer insulation layer with a trilayer barrier layer comprising a titanium silicide layer, titanium silicide layer formed on the titanium silicide by collimation sputtering, and a thermally nitrided titanium formed on the titanium nitride layer. The use of a trilayer barrier layer enables through the capacity of the collimation sputtering apparatus to be increased, prevents particles from occurring, and formation of a low resistance electrical connection between conductors, in addition to preventing diffusion from the titanium nitride layer and the second titanium layer to the thermally nitrided titanium layer, and between conductors.

Highly oriented multilayer film.

Abstract: An oriented multilayer film comprises a barrier layer of polymerized ethylene vinyl alcohol, and an orientation-compatible polymeric layer having a modulus of at least about 4×10 4 psi. The a barrier layer occupies from about 2 to 15 volume percent of the oriented multilayer film, and has a thickness of from about 0.01 to 0.75 mils. The polymerized ethylene vinyl alcohol has an ethylene content of from about 38 to 48 weight percent. The orientation compatible layer has a thickness of from about 0.49 to 4.5 mils. The multilayer film is oriented at a temperature of from about 165° F. to 212° F., has an orientation ratio greater than 9, an oxygen permeability at 0% relative humidity of from about 1 and 6 cm 3 -mil/day-m 2 -atm, and a total thickness of from about 0.5 to 5 mils.

Thermoformable barrier nonwoven laminate

Abstract: The present invention provides a barrier laminate (10) having a barrier layer (12) and a lofty crimped-fiber nonwoven web layer (14), which laminate provides a foam-like resiliency, cloth-like texture and liquid barrier property. The barrier layer of the laminate is selected from films, microfiber nonwoven webs and laminates thereof, and the crimped-fiber web layer, which contains a structural fiber component and a heat-activatable adhesive component, has substantially uniformly distributed interfiber bonds. Additionally provided are thermoformed articles (22) from the laminate and a thermoforming process for producing the articles.

Hall-effect magnetic sensor and a thin-film magnetic head using such a hall-effect magnetic sensor

Abstract: A thin film magnetic head includes a layered semiconductor body formed of a quantum well layer sandwiched by first and second barrier layers, wherein at least one of the first and second barrier layers includes therein a delta-doped layer that shields the quantum well layer from a surface depletion region extending from the surface of the barrier layer.

Semiconductor device having first and second stacked semiconductor layers, with electrical contact to the first semiconductor layer

Abstract: A semiconductor device (e.g., hetero-junction field-effect transistor) which has decreased capacitance between the gate and drain, and which has decreased source resistance, is provided. Structure in which a contact layer 6 comes in contact with the side surfaces of a channel layer 3 but does not come in contact with the side surfaces of a barrier layer 4 enables capacitance between the gate and drain to be decreased. This capacitance can be decreased down to 1.5 pF per 10 μm of the width.

Method for optimizing thermal budgets in fabricating semiconductors

Abstract: The present invention teaches a method for fabricating semiconductors. The method initially comprises the step of forming a conformal layer superjacent at least two conductive layers. The conformal layer preferably comprises tetraethylorthosilicate ("TEOS") and has a thickness of at least 50 Å. Subsequently, a barrier layer is formed superjacent the conformal layer to prevent subsequent layers from diffusing into active regions. The barrier layer preferably comprises Si3 N4, though other suitable materials known to one of ordinary skill in the art may be employed. Further, a glass layer is then formed superjacent the barrier layer. The glass layer comprises at least one of SiO2, phosphosilicate glass, borosilicate glass, and borophosphosilicate glass, and has a thickness of at least 1 kÅ. Upon forming the glass layer, the glass layer is heated to a temperature of at least 800° C. for at least 15 minutes while introducing H2 and O2 at a substantially high temperature to cause vaporization, thereby causing the glass layer to reflow. Next, the glass layer is exposed to a gas and radiant energy for approximately 5 seconds to 60 seconds, thereby making said glass layer substantially planar. The radiant energy generates a temperature substantially within the range of 700° C. to 1250° C. Further, the gas comprises at least one of N2, NH3, O2, N2 O, Ar, Ar-H2, H2, GeH4, and a Fluorine based gas.

Method for forming a capacitor with electrically interconnected construction

Abstract: A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing an electrically conductive first layer over the node; c) providing an electrically insulative barrier second layer over the first conductive layer; d) providing a third layer over the electrically insulative barrier layer, the third layer comprising a material which is either electrically conductive and resistant to oxidation, or forms an electrically conductive material upon oxidation; e) providing an insulating inorganic metal oxide dielectric layer over the electrically conductive third layer; f) providing an electrically conductive fourth layer over the insulating inorganic metal oxide dielectric layer; and g) providing an electrically conductive interconnect to extend over the second insulative layer and electrically interconnect the first and third conductive layers A capacitor construction having such a dielectric layer in combination with the barrier layer and electrical interconnect of a first capacitor plate is disclosed

A conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (eg TiN 50), an noble-metal-insulator-alloy barrier layer (eg Pd-Si-N 34) overlying the oxidizable layer, an oxygen stable layer (eg platinum 36) overlying the noble-metal-insulator-alloy layer, and a high-dielectric-constant material layer (eg barium strontium titanate 38) overlying the oxygen stable layer The noble-metal-insulator-alloy barrier layer substantially inhibits diffusion of oxygen to the oxidizable layer, thus minimizing deleterious oxidation of the oxidizable layer

Cross-linked polyethylene cable insulation

Abstract: An electrical cable for use in submersible well pumps in oil and gas well environments is provided having an electrical conductor core which is surrounded by an insulating layer of cross-linked polyethylene. A barrier layer surrounds the cross-linked polyethylene insulating layer. The barrier layer is impermeable to oil and other liquid hydrocarbons, but is permeable to low molecular gases. The barrier layer is preferably formed from a fluoropolymer and is surrounded by a polymeric protective layer. An adhesive layer attaches the barrier layer to the insulating layer.

Salinity variability in the surface layer of the tropical western Pacific Ocean

Abstract: Observations of surface layer salinity and temperature, rainfall, wind and upper ocean currents from two surveys during the Tropical Ocean Global Atmosphere-Coupled Ocean-Atmosphere Response Experiment are presented. The surveys covered a region of 25×25 n. mi (46.3×46.3 km) with hydrographic sections of 5 n. mi (9.3 km) separation, using a Seasoar towed conductivity-temperature-depth profiler. One survey was dominated by the presence of several rain-induced patches of low-salinity water with slightly reduced temperature. These patches extended to the bottom of the mixed layer, which at the time, was 20–30 m deep, and appeared to be the result of convection driven by their reduced temperature. Below the mixed layer was a 15 to 20 m thick barrier layer. By distributing the freshwater over the mixed layer almost instantly, the convecting patches appeared to contribute to the maintenance of the barrier layer. This survey is typical for conditions found during most of the observation period. The second survey was dominated by a salinity front and advection of low-salinity water with the large-scale westerly wind that prevailed at the time. A single event of very heavy rain produced a shallow lens of freshened water; but the reduction in salinity was so strong that the associated cooling was insufficient to initiate convection. No barrier layer was seen ahead of the front but the observations indicate the development of a barrier layer after the passage of the front. The work demonstrates the difficulties in establishing a freshwater budget for the tropical ocean. Ship borne rain gauge measurements, even though becoming more accurate, seem not to be representative for an area much beyond a few kilometers or less. Sometimes the surface salinity distribution shows better visual correlation with the wind gust pattern than with the rainfall distribution, indicating that the wind gusts associated with atmospheric convection cells are less intermittent and more coherent in space than the rain.

Peelable barrier layer VSP package, and method for making same

Abstract: A method for packaging a product includes the steps of providing a composite film including a non-barrier layer and a peelable barrier layer; providing a bottom web having the product supported thereon; removing a strip of the non-barrier layer from an edge of the composite film so as to provide an extending portion of the barrier layer which extends beyond the non-barrier layer; and sealing the composite film over the product to the bottom web so that the non-barrier layer overwraps the product and is sealed to the bottom web wherein the extending portion of the barrier layer forms a pull tab for peeling the barrier layer from the non-barrier layer.

Method of making a low-resistance contact to silicon having a titanium silicide interface, an amorphous titanium nitride barrier layer and a conductive plug

Abstract: This invention constitutes a contact structure incorporating an amorphous titanium nitride barrier layer formed via low-pressure chemical vapor deposition (LPCVD) utilizing tetrakis-dialkylamido-titanium, Ti(NMe2)4, as the precursor. The contact structure is fabricated by etching a contact opening through an dielectric layer down to a diffusion region to which electrical contact is to be made. Titanium metal is deposited over the surface of the wafer so that the exposed surface of the diffusion region is completely covered by a layer of the metal. At least a portion of the titanium metal layer is eventually converted to titanium silicide, thus providing an excellent conductive interface at the surface of the diffusion region. A titanium nitride barrier layer is then deposited using the LPCVD process, coating the walls and floor of the contact opening. Chemical vapor deposition of polycrystalline silicon, or of metal, such as tungsten, follows, and proceeds until the contact opening is completely filled with either polycrystalline silicon or metal.

Method of forming self-aligned twin tub CMOS devices

Abstract: The present invention provides a method of manufacturing twin wells in a silicon substrate which uses only one photo step and provides a smooth surface topology. The first embodiment begins by forming spaced field oxide regions in the substrate. The spaced field oxide regions define a first region and a second region. A masking layer composed of borophosphosilicate glass (BPSG) and a barrier layer are formed over the field oxide regions. The barrier layer and the masking layer over the first region are removed by a photo etch process. Then, N-type impurities are implanted into the first region forming a n-well using the barrier layer and masking layers as a mask. Then, p-type impurities are implanted into the substrate to form a p-type layer beneath the N-well and a P-well in the second region. The barrier layer and the masking layer are then removed. The substrate is then annealed to drive in the ion implanted impurities thereby forming a n-well and a p-well. A first embodiment uses a barrier layer formed of silicon nitride and a second embodiment uses a barrier layer formed of amorphous silicon.

Method of making an antifuse metal post structure

Abstract: A method of forming an antifuse device. According to the preferred method of the present invention, a first metal layer comprising a first bulk conductive layer and the top capping layer is formed. Next, the capping layer is etched into a first patterned capping layer. An antifuse layer is then formed over the patterned capping layer and over the first bulk conductive layer. Next, a second metal layer comprising a bottom barrier layer and a second bulk conductive layer is formed on the antifuse layer. The second metal layer and the antifuse layer are then etched to form a metal post on the capping layer. The first bulk conductive layer is then etched in alignment with the patterned capping layer to form a first metal interconnect.