Showing papers on "Bit plane published in 1995"

Code division multiple access system providing variable data rate access to a user

Abstract: A multi-code code division multiple access system allows a user at a radio transmitter unit to dynamically change its source data bit rate. In response to a user input selecting one of said plurality of source bit rates, an adjustable coding means in the transmitter spreads and transmits the user's digital bit stream received at the selected bit rate to a channel bit rate which at least equals the highest bit rate of said plurality of source bit rates. The plurality of source bit rates includes a basic bit rate R and at least one bit rate which is a multiple M of the basic bit rate R, where M is an integer of at least 1. The user's input selects a particular user source bit rate by identifying a basic bit rate multiple M to a base station that is to receive the transmission.

Method for reducing temporal artifacts in digital video systems

Abstract: A method and system for improved display of digital video data. The data is arranged into bit planes according to the binary weight of each bit per pixel. The bit planes are then translated into non-binary weighted bit planes by bit translation circuitry (22). These non-binary bit planes are transmitted to the activation circuitry of a spatial light modulator array (30), such that each non-binary bit is displayed at symmetrical times around at least one predetermined point within a video frame time, eliminating visual artifacts associated with binary pulse-width modulation.

Instruction dependency chain indentifier

Abstract: A method and apparatus for identifying a sequence of instructions that generate data used by an instruction in a programmed flow of instructions includes a bit array of i lines, where i is an integer, each line representing an instruction in an ordered sequence of instructions. A line in the bit array is made up of a string of bits in which a bit position is set corresponding to a preceding instruction that the instruction is dependent upon. Logic coupled to the bit array generates the string of bits for the next instruction by setting bit positions which correspond to directly dependent instructions and additional bit positions corresponding to the predecessor instructions.

Coded Domain Picture Composition for Multimedia Communications Systems

Abstract: Video composition techniques are disclosed for processing video information from a plurality of sources to provide a video image having a plurality of rectangular regions Each rectangular region displays video information from a specific one of the plurality of video sources The video information from each video source is in the form of an incoming digital bit stream The digital bit stream from a first video source has a first bit rate, and the digital bit stream from a second video source has a second bit rate where the first bit rate may or may not be equal to the second bit rate The incoming digital bit streams are fed to a rate matching circuit which converts all incoming digital bit streams to a common bit rate The output of the rate matching circuit is fed to a synchronization arid multiplexer circuit which places video information from specific digital bit streams into corresponding rectangular regions of a composite video image

Variable bit rate encoding

Abstract: A rate control algorithm for an MPEG-2 compliant encoder has embodiments useful for constant bit rate and variable bit rate encoding. In particular, the present invention relates to variable bit rate encoding.

Data receiver, method of calculating metrics, and signal processing device

Abstract: A hardware-efficient data receiver in which the receiver digital baseband signal samples relate to the bits in the transmission signal. For each sample, a metric calculator calculates an input data element (metric) for the soft decision decoder in the receiver. The metric is a binary word of whose most significant bit (gross bit) indicates the most likely value (`0` or `1`) of a bit in the transmission signal. The other bits of the metric (reliability bits) express the reliability of this gross bit. The metric calculator has a monotonous transition function with equidistant steps between two extreme metric values (all metric bits are `0` or `1`). According to this transition function, the metric value varies as a function of the digital baseband signal sample value in a range bounded by two saturation values. The number of different sample values in this range, including the saturation values, is two to the power of an integer. Within this range, the reliability bits may readily be derived from a selected number of bits in the binary representation of a digital baseband sample.

Fast serial data transmission using a CRT

Abstract: Disclosed herein is a system and method of serially transferring a sequence of data bits between a computer and a portable information device such as the Timex Data Link™ watch, using the CRT of the computer as a transmission medium. The computer is programmed to display sequential display frames on a frame-scanning graphics display device and to illuminate line segments within the display frames to represent individual data bits. Each line segment has a continuous length on the display device which produces an optical pulse of a corresponding duration. Each data bit is encoded as a different line segment length to produce an optical pulse for each data bit having a duration which is dependent on the value of the data bit. For example, a pulse representing a binary value of 0 has a duration which is relatively longer than that of a pulse representing a binary 1. A receiving device monitors the optical signal created by the CRT and detects rising signal edges. It interprets each rising edge as the beginning of a single bit. After detecting a rising edge, the receiving device waits for a pre-determined time and then samples the optical signal. If the pulse from the CRT is still present, the receiving device interprets the data bit as a binary 0. Otherwise, the receiving device interprets the data bit as a binary 1.

Demodulator for powerline carrier communications

Abstract: A method for demodulating the carrier signal of powerline communication networks. The method involves demodulating an HDLC data body that had been modulated through differential phase shift keyed modulation. Under the method, the data body is split with data input into a single bit digital delay circuit which outputs a delayed or "previous" binary data bit. A "present" binary data bit is input to one input of an XNOR circuit and the previous binary data bit is input into a second input of the XNOR circuit. When the present binary data bit and the previous binary data bit have unlike phases the XNOR circuit outputs a first binary data bit value. When the present binary data bit and the previous binary data bit have like phases, the XNOR circuit outputs a second binary data bit value. Preferably, the demodulated data is input into a post detection filter. The demodulation method also preferably involves the step of processing the demodulated data through a receive data correlator, a data body state machine and a variable divide counter.

A new algorithm for BTC image bit plane coding

Abstract: A new look-up table technique for the coding of the block truncated image bit plane is presented which yields better images in the subjective as well as in the mean square sense compared to the one proposed by Mitchell and Delp (1980). >

Apparatus and method for detecting programmable length bit pattern in serial digital data stream

Abstract: A programmable digital bit pattern detector detects the presence of a variable length, variable content M-bit serial bit pattern that is sequentially repeated in a digital bit stream during some prescribed time constraint, and indicates whether successive repetitions of the pattern satisfy a prescribed criterion, before declaring that the pattern has been successfully acquired. For this purpose, a variable length shift register is programmed with a copy of the pattern. During initial acquisition, in response to a match between a respective bit of the digital bit stream and the content of a selected stage of the shift register, the contents of the shift register are shifted by one bit stage; in response to a mismatch, clocking of the shift register is inhibited for that bit. Count signals are generated in association with successive pluralities of the M bits of the digital bit stream, and an "up/down" counter is incremented or decremented by the count signals, in accordance with whether successive bits of the digital bit stream match the copy of the bit pattern being clocked through the shift register. A maximum pattern match code representative of a prescribed bit error rate and time interval is programmed into a comparator and is compared with the contents of the "up/down" counter. The comparator generates a `pattern acquired` output, in response to the value of the "up/down" counter reaching the value of the maximum pattern match code.

Non-volatile semiconductor memory device using folded bit line architecture

Abstract: A non-volatile memory device which enables use of a folded bit line system includes odd and even main bit lines, a plurality of sub-bit lines connected to the main bit lines through selection gates. Conductive and non-conductive states of the selection gate connecting to the odd main bit line and the selection gate connecting to the even main bit line are controlled by different selection signal lines so that the odd main bit line and the even bit line are operated selectively.

Semiconductor memory with hierarchical bit lines

Abstract: A semiconductor memory with hierarchical bit lines has a plurality of local bit lines, a plurality of global bit lines, a plurality of word lines, a plurality of memory cells each arranged at a connection portion between each local bit line and each word line, and a plurality of transfer gates. The local bit lines are connected to the global bit line through the transfer gates, which are arranged around the centers of the local bit lines. Further, the semiconductor memory has a dummy bit line portion having a dummy bit line that is charged up to a precharging reference voltage during a standby period and is set to a floating state during an active period, to provide the sensing reference voltage. In addition, the semiconductor has sense amplifiers each being formed in an area matching with the interval of a given number of the global bit lines and each receiving signals from a pair of the global bit lines arranged on both sides thereof.

Depth-first coding for multivalued pictures using bit-plane decomposition

Abstract: A data compression technique using a bit-plane decomposition strategy of multivalued images is described. Although the bit-plane decomposition is mainly used for image transmission, our method takes the image expression for image database into consideration. It has two merits which are a hierarchical representation using depth-first (DF) expression and a simple noise reduction algorithm for the DF expression that is similar to human perception. The DF expression is useful for image expansion, rotation, etc. We study the information in an image that should be eliminated by noise reduction. Noise-like patterns in an image are uniformalized and the edge and smooth surfaces remain nearly unchanged. They are not blurred, but instead are a little enhanced. We also study the properties of the black-and-white (B/W) boundary points on bit-planes. The algorithm of the uniformalization process with a DF-expression of an image is described. An experiment for real image data is carried out by a comparison to other methods, and the results are discussed. >

Apparatus and method for encoding and reconstructing image data

Abstract: An apparatus for processing an input image, represented by an input bit stream including a plurality of first bit sets, is provided. The apparatus includes a device for processing the input bit stream in such a manner that each of the first bit sets is represented by a second bit set with each of the second bit sets having less bits than each of the first bit sets and a selected number of bits in the input bit stream, corresponding to image-related information, being discarded as a result of the encoding. The apparatus is provided with an electronic volatile memory for storing a resulting encoded bit stream and a bit stream analyzer for analyzing the stored encoded bit stream to generate positional signals. The apparatus is further provided with a reconstruction circuit for reconstructing the stored encoded bit stream, by reference to the positional signals. The reconstruction circuit operates in such a manner that, upon outputting an image representation of the reconstructed bit stream, the outputted image includes at least a part of the discarded, image-related information.

Method and apparatus for data encoding and data recording medium

Abstract: A data encoding method apparatus in which the volume of arithmetic-logical operations for calculating the total number of bits required for encoding for adaptive bit allocation in the variable length encoding system for expediting the processing. In the data encoding apparatus for encoding and subsequently variable length encoding the input data, spectral data obtained on orthogonal transform coding are routed to a block floating circuit 403 for normalization and re-quantized in a quantization circuit 404 depending on the bit allocation number information from a bit allocation calculating circuit 406 so as to be then variable length encoded by an encoding circuit 407 and outputted at an output terminal 408. The bit allocation circuit 406 refers to a table memory circuit 409 in which re-quantized data domain is divided at boundary points corresponding to code length transitions in order to calculate the total number of bits required for encoding using a smaller volume of arithmetic-logical operations for the purpose of adjusting the number of allocated bits.

Circuit structure and method for stress testing of bit lines

Abstract: A plurality of bit lines is arranged in columns and grouped into a first set of bit lines and a second set of bit lines. Each bit line in the first set of bit lines alternates with each bit line in the second set of bit lines. First switching means electrically connects the first set of bit lines to a first voltage level and, simultaneously, second switching means connects the second set of bit lines to a second voltage level. This permits a bit line stress test that will reveal defects or failures in a memory chip.

Semiconductor memory device having bit line equalizing means

Abstract: A semiconductor memory device having memory cells arranged in a matrix, each of the memory cells having input/output terminals, word lines for selecting the memory cells, pairs of bit lines connected to the input/output terminals, bit line pulling-up means for pulling up the potential of the bit lines, bit line loading means connected to another pair of bit lines and bit line equalizing means provided for the bit lines for equalizing the potential of the bit lines by allowing conduction between the bit lines before data is read from a selected memory cell.

Information recording method and device

Abstract: A method of recording a bit stream on a Phase Change media by illuminating a laser beam on the Phase Change media includes assigning a predetermined number of channel bits to each bit of the bit stream, and assigning one of a highest power level, an intermediate power level, and a lowest power level of the laser beam to each of the channel bits so as to modulate the laser beam, wherein an arrangement of the highest power level, the intermediate power level, and the lowest power level for one bit of the bit stream depends on values of the one bit and an immediately preceding bit.

Encoding system and encoding method for encoding a digital signal having at least a first and a second digital component

Abstract: An encoding system and an encoding method for encoding a digital signal having at least a first and a second digital signal component. The encoding system comprises splitter means (2, 12) for dividing the bandwidth of the digital signal components into M successive frequency bands, and generating in response to the digital signal components M sub signals (SBml, SBmr) for each digital signal component, each sub signal of a signal component being associated with one of the frequency bands (m), bit need determining means (16) for determining bit needs for time equivalent signal blocks of the sub signals, signal combination means (25, 26, 27) for combining, in a number of at least one frequency bands, time equivalent signal blocks of corresponding sub signals of the at least first and second signal component so as to obtain a time equivalent signal block of a composite sub signal in each said at least one frequency bands, quantizing means (Qml, Qmr, 32.j) for quantizing time equivalent signal blocks of the sub signals in those frequency bands in which no composite sub signal is available and for quantizing the corresponding time equivalent signal blocks of the composite sub signal in said at least one frequency bands in which a composite sub signal is available. Further, bit allocation means (7) are available for deriving the allocation information (nmi, njc) from bit needs obtained in the bit need determining means and from a value B, where B corresponds to a number of bits in an available bitpool. The bit need determining means (16) is adapted to determine a common bit need bmc for a time equivalent signal block of a composite sub signal SBmc in a frequency band m from the bit needs bmi of the time equivalent signal blocks of the corresponding sub signals of the at least two signal components in that frequency band from which the time equivalent signal block of the composite sub signal has been derived, by taking the common bit need bmc equal to a weighted sum of the bit needs bmi. The encoding system can be a subband encoding system or a transform encoding system.

Method for driving bit line selecting signals

Abstract: A method for driving bit line selecting signals is disclosed, in which the DRAM cell includes a plurality of memory cell arrays, sense amplifiers, bit lines, bit line equalizer sections, bit line selecting sections, data input/output sections, and bit line selection signal generating sections. According to the present invention, the bit line selecting signals operate in such a manner that: during a bit line selection, a bit line selecting signal for connecting one pair of bit lines among the n pairs of bit lines to the sense amplifier is made to have a voltage level capable of connecting the bit lines to the sense amplifier by the help of the bit line selecting section without a voltage loss; the other bit line selecting signals corresponding to the non-selected remaining bit lines are given a voltage incapable of connecting the bit lines the sense amplifier by the bit line selecting section; thereafter, during the pre-charging for a bit line equalization, the bit line selecting signal corresponding to the bit line which was selected just before is given a voltage capable of connecting the bit lines to the sense amplifier by the help of the bit line selecting section; and the bit line selecting signals which do not correspond to the bit line selected just before are maintained without a voltage shifting.

Synchronizing signal detection apparatus

Abstract: A synchronizing signal detection apparatus of the present invention comprises a demodulator for digitally demodulating input signals, a partial matching error counter for comparing every bit of the demodulated input signal bit pattern demodulated by said demodulator with a part of the known synchronizing signal bit pattern. The apparatus further comprises a remaining bit matching counter for comparing the input signal bit pattern with remaining bits of the synchronizing signal bit pattern used in the partial matching error counter, or with all synchronizing signal bit pattern, for every bit, when an error bit number, which is compared in the partial matching error counter, is equal or less than a first threshold value. When the error bit number compared in the remaining bits matching error counter is equal or less than a second threshold value, synchronizing signal is assumed to be detected. In the apparatus of the present invention, bit pattern comparison numbers are decreased.

Efficient packed encoding method for ASN.1

Abstract: An efficient packed encoding rules (EPER) for ASN.1 for efficiently encoding the value to each type of abstract syntax definition, in which structure of an encoding data is divided into three fields of a bit field, an octet field following the bit field, and an offset field selectively added to before the bit field, in the bit field, bit data is set in the order of the abstract syntax definition, in the octet field, octet data in a unit of octet is set in the order of the abstract syntax definition, in the offset field, a length information of bit field is set and, in the bit field, padding is made so that a total length of the offset field and the bit field is an integer multiple of 8 bits, and the offset field is added when the length of bit field is not determined from the abstract syntax definition, thereby eliminating problems of PER.

Picture composition with coded picture data streams for multimedia communications systems

Abstract: Video composition techniques are disclosed for processing video information from a plurality of sources (101-104) to provide a video image (150) having a plurality of rectangular regions. Each rectangular region displays video information from a specific one of the plurality of video sources. The video information from each video source (101-104) is in the form of an incoming digital bit stream. The digital bit stream from a first video source has a first bit rate, and the digital bit stream from a second video source has a second bit rate where the first bit rate may or may not be equal to the second bit rate. The incoming digital bit streams are fed to a rate matching circuit (109-112, 121-124, 129-132) which converts all incoming digital bit streams to a common bit rate. The output of the rate matching circuit is fed to a synchronization and multiplexer circuit (147) which places video information from specific digital bit streams into corresponding rectangular regions of a composite video image (150).

Method of and apparatus for RDS phase synchronization on the receiver side

Abstract: A method of phase synchronization of a bit rate clock signal generated on a receiver side with a biphase-modulated digital RDS signal that is demodulated on the receiver side with both signals having the same bit rate. The bits of both the RDS signal and the bit rate clock signal are each composed of two half bits having different digital potential values. The first or the second RDS half bit has a high digital value and the other RDS half bit has a low digital value based on which one of two logic values "1" and "0" is represented by the respective RDS bit. At a first time coinciding with the time of a rising and/or falling edge of a bit of the RDS signal, the digital value of the bit rate clock signal is measured as a first sample value, and at a second time shifted from the first time by a delay time that is shorter than a half bit duration, the digital value of the bit rate clock signal is measured as a second sample value. The phase position of the bit rate clock signal is shifted by a positive or a negative phase angle of a phase angle amount based on whether the two sample values each have a different or an identical digital value.

Preprocessing multiple bit per pixel sampled data for Lempel-Ziv compression

Abstract: A preprocessor for processing sample data, particularly digital video data, to improve lossless sliding window type Lempel-Ziv compression of the data. Sliding window Lempel-Ziv compression is improved by transposing the multiple bit per pixel data samples before compression so that the relatively repetitive higher order bits of successive pixels are compressed separately from the relatively volatile lower order bits of the successive pixels. The transposition is particularly suited for bit plane configured frame buffers in that compression and decompression grouping is readily performed by the manipulation of data within the individual bit planes.

Variable bit rate coder

Abstract: PROBLEM TO BE SOLVED: To obtain a variable bit rate coder by obtaining a subject evaluation value corresponding to a coding bit rate, conducting prescribed processing based thereon, and coding optimizingly the entire image quality while keeping the average bit rate to be a prescribed value. SOLUTION: A variable bit rate coding section 2 encodes digital image data 1 for a prescribed time length for each variable bit rate so that the average bit rate is a specified value or below. A subject evaluation section 4 obtains a subject evaluation value corresponding to the different coding bit rate for each unit time being division of the digital image data 1 for a prescribed time. A bit rate allocation section 5 decides the bit rate for each unit so that the average bit rate is an object rate or below based on the obtained subject evaluation value and the desired evaluation of the entire image quality is optimum. Thus, optimum bit rate arrangement is attained with respect to image data in each unit time under a prescribed condition.

Apparatus for generating a digital recording signal which avoids the generation of false synchronization bit patterns

Abstract: In a digital information modulating apparatus, first information signal is separated every m bit or bits, and n bit or bits are added to the head of every m bit or bits to change every m bit or bits of the first information signal into every m+n bits of a second information signal, where "m" and "n" denote predetermined natural numbers. The second information is pre-coded into plural pre-coded information signals in accordance with combinations of the added n bit or bits. A determination is made as to whether or not predetermined sync information is present in the pre-coded information signals. A sync detection signal is generated which represents the result of the determination. One of the pre-coded information signals is selected as a modulation-resultant output signal in response to the sync detection signal.

Digital dividing apparatus using a look-up table

Abstract: The digital dividing apparatus includes a comparator (3) for comprising a first input signal A with a second input signal B; a selector (4) responsive to an output from the comparator for selecting larger one out of the first and the second input signals; a priority encoder (5) for outputting a priority signal in which only a bit corresponding to the most significant bit out of bits indicating 1 of the selected input signal indicates 1; a bit difference encoder (6) responsive to the priority signal for outputting a bit difference between the most significant bit of the selected input signal and the most significant bit out of bits indicating 1 of the selected input signal; a first shifter (7) for shifting the first input signal A to an upper side by the bit difference; a second shifter (8) for shifting the second input signal B to an upper side by the bit difference; a first round down circuit (9) for rounding down lower bits of the signal shifted by the first shifter to produce a first m bit round down signal α; a second round down circuit (10) for rounding down lower bits of the signal shifted by the second shifter to produce a second n bit round down signal β; an LUT memory (11) for pre-storing a look up table; and an LUT control circuit (12) for controlling the LUT memory.

Color facsimile equipment

Abstract: PURPOSE:To obtain facsimile transmission data in which black level reproducibility is enhanced with excellent compression efficiency. CONSTITUTION:Each component of RGB image data comprising picture elements received by a scanner 7 is checked and whether the checked picture element is a black level picture element or a color picture element is discriminated. The RGB data as to the color picture element are converted into XYZ space data, and the data are converted into color (binary) data having no color tone by using a chromaticity diagram of an XYZ space. Information of a black picture element and color information obtained in this way are expanded to a bit plane of a bit map memory 3b corresponding to the color. Then the image data are compressed for each bit plane and the compressed data are sent.