Showing papers on "Block (data storage) published in 1983"

A Data Flow Oriented Program Testing Strategy

Abstract: Some properties of a program data flow can be used to guide program testing. The presented approach aims to exercise use-definition chains that appear in the program. Two such data oriented testing strategies are proposed; the first involves checking liveness of every definition of a variable at the point(s) of its possible use; the second deals with liveness of vectors of variables treated as arguments to an instruction or program block. Reliability of these strategies is discussed with respect to a program containing an error.

Interframe coding apparatus

Abstract: An interframe coding apparatus performs motion detection and vector quantization on the basis of a block of interframe differential signals and includes a vector quantizer. The data of the interframe differential signal or the block scanning predictive error signal is compressed using a vector quantizer. The vector quantizer receives a plurality of suppressed predictive error signals (624) as input signals in block form and operates to form input vectors. The data is analysed by a motion detector (652) and where motion is detected, the relevant block is coded as a significant block. A coder (638-642) operates to determine an output vector having the least distortion with respect to an input vector by various techniques. A coded output or output vector codetable address (625) is output from the coder of the device for receipt by a decoder (639,642,654,655) which constructs a proper output vector signal.

Image storage and retrieval

Abstract: An improved technique is presented for organizing digitized information for storage in a relational type tree memory structure where the digitized information is broken up into blocks of a fixed byte size which are then stored throughout the memory. A header is utilized which identifies a text or image and details of how the image was digitized and compressed, to be used in reconstructing the image properly. We also utilize an index in which is the image or text identity but also in which is an index identifying the locations throughout memory at which the blocks containing the text or image information is stored. Each block has a header identifying what text or image information is stored in the block and having the address of any another block containing realsted information for the same text or image to thereby create a chaining between the blocks by which they may all be quickly located once a first block is located using the index. A further embodiment of invention allows the storing and display of a base image containing user defined and located subfields and the selective insertion of related data or images, either previously stored or entered by the user, into the subfields. A yet further embodiment allows the use of data contained in the subfields as keys to locate and display further related information.

Estimating block transfers and join sizes

Abstract: In this paper we provide estimates of the number of sequential and random block accesses required for retrieving a number of records of a file when the distribution of records in blocks of secondary storage is not uniform. We show how these results apply to estimating sizes of joins and semi-joins. We prove that when the uniformity of placement assumption is not satisfied it often leads to pessimistic estimates of performance. Finally we show a recursive estimation of the probability distribution of the number of blocks containing a given number of records.

Set associative sector cache

Abstract: A cache memory (10) for a data processing system having a tag array (22) in which each tag word can contain a sector address (A18-A31) and represents a predetermined set or block group of consecutively addressable data block locations in a data array (26). The lower order set address bits (A8-A17) concurrently access the tag word and its associated group of block locations in the data array while individual blocks within the group are accessed by supplemental block bits (A6-A7). Each tag word read out must compare equal (28) with the high order sector bits (A18-A31) of the address and an accompanying validity bit (Vi) for each accessed block location in its group must be ON in order to effect (30) a hit. Also described are circuits for writing into the cache and adapting the cache to a multi-cache arrangement.

Estimating block accesses in database organizations: a closed noniterative formula

Abstract: Authors' Present Addresses: Kyu-Young Whang and Gio Wiederbold, Computer Systems Laboratory, Stanford University, Stanford, CA 94305; and Daniel Sagalowicz, Artificial Intelligence Center, SRI International, Menlo Park, CA 94025. This work was supported by the Defense Advanced Research Project Agency under the KBMS Project, Contract N39-80-G-0132. Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the publication and its date appear, and notice is given that copying is by permission of the Association for Computing Machinery. To copy otherwise, or to republish, requires a fee and/or specific permission. © 1983 ACM 0001-0782/83/1100-0940 75¢ 1. I N T R O D U C T I O N In eva lua t ing the access cost o f a q u e r y for a da tabase organiza t ion in w h i c h records are g rouped into b locks in s e c o n d a r y storage [16], one m u s t o f ten es t ima te t he n u m b e r of b lock assesses r equ i r ed to re t r ieve t h e records se lec ted by t h e query . Var ious fo rmulas h a v e b e e n p roposed for this pu rpose [2, 3, 8-13, 17, 19]. In part icular , Yao [17] p r e s e n t e d the following theo rem: 1

Non-volatile memory device

Abstract: PURPOSE:To decrease the number of times of replacement of a memory and to improve the reliability, by splitting a non-volatile memory having a storage capacity of plural times of that of a system to each block and providing an exclusive location of the number of times of write for each unit block. CONSTITUTION:A storage area of an EEPROM having a capacity >=2 times the capacity requested to the system is splitted to blocks 1 and 2, and the direction of split is taken in the direction of word arrangement. Exclusive locations 3, 4 to store the number of times of program write to the corresponding memory are allocated to the blocks 1, 2 respectively, and the number of bits of each location corresponds to the limit value of the number of times of program write of the corresponding memory. When the number of times of program write of the block 1 reaches a specified value, the block is used switchingly. Whether or not the number of times of write reaches the specified value is discriminated with a count value stored to the locations 3, 4.

A storage scheme for extendible arrays

Abstract: Conventional methods of storing aK-dimensional array allow easy extension only along one dimension. We present a technique of allocating a linear sequence of contiguous storage locations for aK-dimensional extendible array by adjoining blocks of (K−1)-dimensional subarrays. Element access is by determination of the block header location and then the displacement within the block. For cubical and all practical cases of rectangular arrays considered, the storage requirement isO (N) whereN is the array size. The element access cost isO (K) for the 2-step computed access function used.

New methods for dynamic storage allocation (Fast Fits)

Abstract: The classical methods for implementing dynamic storage allocation can be summarized thusFirst Fit and Best FitThe available blocks of storage are linked together in address order. Storage is allocated from the first available block of sufficient length, or from a block with the minimum excess length. Storage can be allocated or released in multiples of two words. In the long run, if numerous pieces of storage of more-or-less random lengths are allocated and released at more-or-less random intervals, the storage becomes fragmented, and a number of uselessly small blocks develop, particularly near the beginning of the list. Although these fragments usually comprise a small proportion of the storage (typically around 10 per cent), a lot of time can be wasted chaining through them.Buddy MethodsHere the task of managing the storage is reduced in size by constraining the way in which the storage can be divided up, e.g. into blocks with lengths which are powers of 2. This eliminates chaining through long lists of uselessly small blocks; on the other hand, space is wasted in rounding up the length requested to an allowable size, and typically about 40 per cent more storage is required to satisfy the same allocations than when using First Fit or Best Fit.The methods presented in this paper are externally compatible with First Fit and Best Fit, and require roughly the same amount of storage for a given sequence of allocations. They use, however, a completely different internal data structure, one effect of which is to reduce the number of blocks that have to be visited to perform a typical allocation or release operation. These new methods exhibit roughly the same space performance as First Fit, and a time performance which falls between those of First Fit and Buddy.

Digital signal transmission system

Abstract: In a digital signal transmission system for effecting time-division multiplexing/circuit switching transmission of data in the form of packets by means of telecommunication cable, a packet configuration and line connection control data inserted in the packets are improved. In phases of the establishment/termination of a call, line connection control data of the overhead field are inserted as repeated at least one time into the data field. At least one set of line connection control data of the overhead field contains a parity bit. A receiving station reads the line connection control data in the overhead field and the data field of a received packet, and determines the overhead data by the principle of decision by majority. After completion of establishment of a call, the receiving station takes in the transferred data out of a block on the basis of a positional information, for example, a number of the block. In the phase of transmission of data, transmitting station inserts additional data bits into at least part of the overhead field in the packet being transmitted.

Time base correcting apparatus

Abstract: A time base correcting apparatus is disclosed which is capable of correcting time base errors contained in a digital signal supplied thereto in the form of successive data blocks with each data block including plural data words. Each data block includes therein at least plural data words and a block address circulating with a predetermined phase relation relative to a certain reference signal. A memory is provided, having plural addressable storage locations, each adapted to store a respective data block. A write-in address to identify the particular storage locations is generated according to data block addresses and read-out addresses. The write-in address is varied by a lock phase mode signal indicative of a phase relation at which an incoming digital signal is locked to a reference signal so that notwithstanding the phase mode in which the digital signal is locked to the reference signal, the correction ability of the time base correcting apparatus can be prevented from being lowered.

Trend-free block designs: existence and construction results

Abstract: Designs for which treatment and block contrasts are orthogonal to specified common trend components within blocks have been called trend-free block designs. A necessary and sufficient condition for the existence of such designs was given in a reference. A matrix sum was required to have certain properties. It is shown now that the existence of a matrix with the required properties assures the existence of the necessary component matrices] The existence of trend-free block designs for specified trends in one or more dimensions is examined in a number of theorems and corollaries. Initial results are general and then trends in one dimension are considered. An alternative formulation of the necessary and sufficient condition for a trendfin one dimension are sufficient condition for a trendfree block design is given when each treatment has the same number of replications. Some special results are obtained for complete and balanced incomplete block designs. Some design construction methods are developed to esta...

Multirate recursive digital filters--A general approach and block structures

Abstract: Multirate filters, in which the input and output sample rates differ, are examined from a general point-of-view with the objective of providing an approach that will permit the filter designer to use input and output sample rates as design variables to be used to optimize system performance. The emphasis is on multirate recursive (IIR) filters that can be computationally efficient when implemented with block structures, with input and output blocks of different lengths. Classes of multirate filters that possess a generalized shift-invariance property, and are susceptible to transfer function analysis, are identified. A general approach to deriving matrix transfer functions for block implementations of multirate filters is derived, and a general method for obtaining state-space realizations of the matrix transfer function is presented.

Input/output system and method for digital computers

Abstract: An input/output (I/O) system and method for coupling a host computer to a plurality of peripheral devices in which data destined for peripheral devices is transferred to an output data buffer whose locations are paired with output channel addresses stored in an output device table. A microcomputer performs any processing required on data stored in the output data buffer by reading the address and a function code in the output device table then distributes processed data to an output device block whose locations are addresses of output channels. An input data buffer and input device table similarly arranged, collects and processes input data continuously, which input data buffer can be transferred to the host computer, on command, in a high speed burst.

Numerical control method and apparatus therefor

Abstract: First and second tool control blocks respectively precede and follow a corner on a tool path. A pulse distribution computation based on NC command data in the second block is not executed at the instant that a pulse distribution computation based on NC command data in the first block ends. Rather, a pulse distribution computation based on the NC command data in the second block is performed starting at the instant that a feed speed based on the NC command data in the first block is reduced to a prescribed speed by being decelerated. As a result, the torch of a gas cutting machine or the like will cut the corner portion quickly with a high degree of accuracy and without cutting the corner to an overly rounded shape.

Path Delay Analysis for Hierarchical Building Block Layout System

Abstract: This paper describes a path delay analysis system which employs an accurate signal delay calculation method for MOS LSIs, taking poly resistance into account. The system takes mask patterns generated by a hierarchical building block layout system as inputs, and verifies timing margins of a large scale random logic LSI in a module-wise bottom up fashion. Path delay analysis using a critical path trace algorithm and an enumerative path trace algorithm in combination is effective in locating critical timing regions in a chip and in analyzing critical paths in the regions in detail.

Digital data storage in video format

Abstract: A method and apparatus for encoding a plurality of bytes of digital data into a further plurality of bits suitable for storage in a storage medium, and for recovery therefrom, and for decoding the stored bits retrieved from the storage medium, for the recovery of the encoded bytes. The digital data bytes are arranged into a plurality of code blocks, each having a first predetermined number of columns and a second predetermined number of rows of bytes. A parity block of bytes of data is generated having a number of columns and a number of rows of bytes corresponding to the first predetermined number of columns and to the second predetermined number of rows of bytes, respectively, of the code blocks, the bits of data in the parity block corresponding to the computed parity of the combined corresponding bits in each of the code blocks. Secondly, a parity row of bytes of data are generated for each of the data blocks such that each bit in each byte in the parity row corresponds to the computed parity of the combined corresponding bits in each byte in the column of the associated data block of that parity row. Each such row of parity bytes is added to its associated block. Thirdly, a correction control word is generated for each 8 bit byte of data blocks, parity rows and parity blocks, and is added to its associated byte to form a composite word. The bits of data of all such composite words for all of the blocks are interleaved according to a matrix having a third predetermined number of rows and a fourth predetermined number of columns, and the interleaved data is provided in serial arrangement for storage.

Apparatus for processing document data including voice data

Abstract: A data processing apparatus permitting editing of document blocks associated with voice block data, wherein various document blocks, stored in a memory section, are read out and displayed on a display. A desired document block is designated by a cursor, and the corresponding voice data is input, thereby associating the desired document block with the corresponding voice block data which is stored in another memory section. Input sentences are divided into document blocks, to be edited and displayed. Even if the document block displayed is moved during editing, the voice data corresponding to the moved document block can be output, by operating a voice output key.

Method for dynamically reconfiguring a data processing system for added devices

Abstract: A method of on-line reconfiguring a data processing system for an added input/output (I/O) device in which a configuration program is called and menus are presented. Based on menu selections, the program causes a device definition to be built. The built definition is used to construct a control block which is stored into main storage during system operation such that the added device is available for use on a real time basis.

Adaptive prediction for binary encoded documents containing a mixture of text, line drawings and halftones

Abstract: This is a circuit and method for adaptively selecting one of a plurality of predictor patterns to encode a stream of image data blocks such as would be output from a raster-input-scanner. A variety of halftone and nonhalftone predictor patterns are used and compared, with the best one being selected to predict the next block. Using this technique, the best predictor pattern is usually selected, predicted data buffering is not needed, and no code need be transmitted with the data to the receiver to specify the predictor to be used in the deprediction process since the same basic information is also available to the receiver.

Block counter system to monitor data transfer

Abstract: A system is disclosed which is usable to monitor data-being-transferred in terms of blocks (512 bytes or 256 words) wherein the data-being-transferred is temporarily stored in a RAM buffer memory. Thus, data blocks being transferred from a main host computer to a peripheral terminal unit (as a magnetic tape unit) via a Tape Control Unit (TCU) can be monitored to indicate, at certain intervals, the balance of data residing in the buffer memory during moments between cycles where data has been shifted into and/or shifted out of the buffer memory.

Data multiplex control facility

Abstract: A data processing system includes a central processing unit (CPU), an input/output microprocessor, a main memory and a number of mass storage controllers. A block of information is transferred between one of the mass storage controllers and main memory during data multiplex control (DMC) cycles. The CPU includes registers which store the address of main memory into which the next data byte is written or read from and the range indicating the number of data bytes remaining to be transferred. Prior to a DMC cycle the CPU stores address and range information in a mailbox location in an I/O RAM and the I/O microprocessor transfers that information to channel table locations in the I/O RAM. For a DMC operation, the I/O microprocessor transfers the address and range information to the mailbox location and transfers the mass storage information to the mass storage controller. It signals a CPU interrupt and issues a read or write order to the mass storage controller. The CPU then retrieves the address and range information from the mailbox location and initiates a DMC cycle.

A Computationally Fast Approach to Maximum-Likelihood Deconvolution

Abstract: In this paper we derive and implement a maximumlikelihood deconvolution (MLD) algorithm, based on the same channel and statistical models used by Kormylo and Mendel (1983a), that leads to many fewer computations than their MLD algorithm.,Both algorithms can simultaneously estimate a nonminimum phase wavelet and statistical parameters, detect locations of significant reflectors, and deconvolve the data. Our MLD algorithm is implemented by a two-phase block component method (BCM). The phase-l block functions like a coarse adjustment of unknown quantities and provides a set of good initial conditions for the phase-2 block, which functions like a fine adjustment of unknown quantities. We demonstrate good performance of our algorithm for both synthetic and real data.

The construction of fast, high-rate, soft decision block decoders

Abstract: A detailed description is given of a fast soft decision decoding procedure for high-rate block codes. The high speed is made possible (in part) by using the symmetries of the code to simplify the syndrome decoding by table look-up and by making the best use of the soft decision information. The (128,106,8) BCH code is used as an example.

Method and system for communicating over an open communication network

Abstract: Method and system for communicating over an open communication network; communication data blocks are provided with a code word with a cyclic numbering for successive blocks to be able to place received block in the correct sequence. By detecting the missing data block and/or an acknowledgement control block with a number added to the data block restoring procedures are preformed. After a successful restoring procedure the number of the originally missed block and or the acknowledgement control block are left out the cyclic numbering for a time at least equal to the warranted maximum packet lifetime in the network.

Coding system for the registration of information on workpiece holders or the like

Abstract: A coding system for recording information on mobile workpieces or workpiece carriers is proposed, which is used to control production processes or other processes that can be automated, in that the information is stored as a bit pattern in an information carrier and can be scanned in a contactless manner by means of stationary sensors. An electronic memory block (24, 40), which has an input for writing information into the memory block and an information output for reading out the memory content by stationary sensors (19, 20), serves as the information carrier (21) (FIG. 1).

Data transfer control system

Abstract: A data transfer control system which is provided between a main memory for storing programs, data and channel control blocks (CCB's) and I/O processors for controlling channels, for converting an address from the I/O processors to an address specifying the main memory, first address memory which is addressed by combination data of a first identification number identifying the I/O processors and a second identification number identifying the channel and stores a CCB start address of the main memory; second address memory which is addressed by the combination data and stores a start address in a data transfer section included in the channel control block; and a data controller in which, when the first and second identification numbers, a flag, and a relative address are received from the channels through the I/O processors, one of the first and second address memories is selected in accordance with the flag value, the data controller generating an address by adding the address read out from the selected memory and the relative address and then sending the added address to the main memory