Showing papers on "Block (data storage) published in 1986"

Disk striping

Abstract: Just like parallel processing elements can substantially speed up computationally intensive tasks, concurrent transfer of data in and out of memory can speed up data intensive tasks. In this paper we study one general purpose facility for achieving parallel data motion: disk striping. A group of disks is striped if each data block is multiplexed across all the disks. Since each subblock is in a different device, input and output can proceed in parallel. With the help of an analytical model, we investigate the effect of striping on disk service times and its advantages and limitations in one of a set representative applications, file processing. We also explore several possible enhancements to striping: immediate reading, ordered blocks, and matched disks.

High resolution color video image acquisition and compression system

Abstract: A digital color video image digitizing and communication process comprises the steps of dividing digital data representing the overall picture information for a video image into sets of data representing shape and color information for blocks of the image with the color information including the major colors for the corresponding block and the variation in shades or hues of the colors within the block, separating, according to a predefined encoding procedure, each of the data sets into a first group of data representing the major colors constituting the block and a second group of data comprising the remaining data in the data sets and representing the shades of the major colors within the block, storing the second group of data in a color table, processing the second group of data and transmitting the first group of data and the processed second group of data to a decoder capable of processing received data according to a predefined decoding procedure, processing the received first data group to display the encoded image in its major colors, and combining the first group of data with the selected data from the second data group and processing the combined data to display the encoded video image with the variations in shades of the major colors. The digitizing process is adapted to operate in a plurality of modes incorporating different encoding/decoding procedures and provides high resolution digitizing of color images while at the same time providing the capability of controlling the degree of compression at the encoding end as well as the decoding end, thereby making it suited to a variety of color image digitizing applications.

Performance Analysis of the Selective Repeat ARQ Protocol

Abstract: Delay, queue length, and throughput are the main performance characteristics of a data transmission system with ARQ (automaticrepeat-request) error control. Various protocols which have been proposed use, as a part or as a whole, the basic selective-repeat ARQ protocol. Their performance analysis has, however, been restricted to the throughput characteristics. An easily applicable method to analyze this basic protocol has not appeared in the literature so far. In this paper, two different methods for the queue length and delay analysis are presented. The system is modeled as a discrete time queue with infinite buffer storage. Transmission errors are considered to be independent, and block arrivals may follow an arbitrary interarrival time distribution. The first method uses an exact Markov state model, on which the theory of absorbing and ergodic Markov chains is applied, and leads to a computational algorithm. The second method, which is based on a specific assumption, uses a substantially simpler stochastic model and results in equations which are easily solved by means of iterative computation. In the case of geometrically distributed interarrival times, simple analytical formulas are extracted. The results are compared to the exact ones (that is, those obtained by the first method or by extended simulation runs) and surprising agreement is observed.

Navigation system for automotive vehicle with automatic navigation start and navigation end point search and automatic route selection

Abstract: A navigation system has a map memory storing map data. The road map stored in the map memory is divided into a plurality of pages further subdivided into continuous blocks. The map memory also stores identification data for the blocks and index data for various points within the map blocks. The index data includes position data for a plurality of known points. The navigation system also includes an input unit for entry of the identification data for a map memory block and/or the index data for known points, and a display unit for displaying a map block on a display monitor. A processor of the navigation system accepts entry of the index data for a travel starting point and a destination through the input unit. Based on the entered data, the processor searches for the map blocks containing the designated known points. The processor progressively expands the search area along a vector between the travel starting point and the destination. The process finds the known point closest to the travel starting point and the other known point closest to the destination along the vector and stores these as the navigation start point and the navigation end point.

Portable electronic device with garbage collection function

Abstract: A portable electronic device of this invention has a control CPU (Central Processing Unit) and a data memory. The data memory is divided into a plurality of areas, and each area consists of a data area and an attribute area indicating an attribute of the data area. The attribute area consists of a first flag indicating whether or not data is stored in the data area, a second flag indicating whether or not data written in the data area is valid, and a third flag indicating whether or not data written in the data area is stored as a block. When an instruction supplied from a host system is a valid-data rearrangement instruction, the control CPU refers to the second flag, and sets a first flag of a data area whose second flag indicates that data is invalid to indicate that data is unwritten, thus rear-ranging valid data of the data memory so that no invalid data area is present between valid data areas. When the third flag indicates write incompletion, the control CPU sets the second flag to make the data area invalid.

Method of optimizing signal timing delays and power consumption in LSI circuits

Abstract: @ A method of optimizing signal timing delays and power consumption through multi-path LSI circuits constructed from a plurality of circuit blocks, each circuit block having associated therewith a plurality of power levels which are selectable to control the timing delays through the circuit block, wherein the method steps include the formation of a power- performance derivative for each circuit block, identifying therefrom the relative contribution to signal delay of the circuit block in the entire multi-path configuration, and selecting the optimum power level for an overall multi-path minimum signal delay condition, through a process of iterative calculation of timing delays through individual circuit blocks and multi-path timing analysis.

Optimal soft decision block decoders based on fast Hadamard transform

Abstract: An approach for efficient utilization of fast Hadamard transform in decoding binary linear block codes is presented. Computational gain is obtained by employing various types of concurring codewords, and memory reduction is also achieved by appropriately selecting rows for the generator matrix. The availability of these codewords in general, and particularly in some of the most frequently encountered codes, is discussed.

Method for image data coding

Abstract: To efficiently compress image data, the image data is divided into rectangular blocks of non-equal length in a hierarchal structure in accordance with a brightness change, and is encoded into tree-structure data for each of the divided blocks so that the mean distortion of the image data inside each block does not exceed an allowable value.

Scientific processor vector file organization

Abstract: A vector file organization for a multiple pipelined vector processor with data transfer capability to support multiple program execution pipelines. Multiple pipelines can simultaneously access various blocks of the vector file through segmenting the file storage and by addressing the various elements of the segments. Vector files of programmable registers each have storage for sixty-four elements of 36-bit words or thirty-two elements of 64-bit words. Six independent execution pipelines in combination can programmably access the vector files for either read operands or write operands or both. Each vector file has N independent blocks, each using a RAM with read output to the pipelines, an address register and a write data register. Each block holds interspersed word pairs of words of each vector file. Primary and secondary vector files are equal in capability and allow reading pairs of elements, as required by arithmetic instructions. Shadow storage similarly arranged and addressed provides storage for intermediate result vectors. A time slot management mechanism uses N registers connected in serial loop, to allocate and reserve access to the vector files by the execution pipe for each instruction execution to maintain its function. It forms a read or write address for both the primary and secondary files and references all N blocks in a pass.

The block-processing FTF adaptive algorithm

Abstract: A new block-type adaptive-filtering algorithm is presented. This new block adaptive filter differs from the frequency-domain block adaptive filters of Ferrara (1980), and of Clark, Mitra, and Parker (1980), in that the new method applies a deterministic time-domain least-squares criteria within each of the data blocks. Information is carried from block to block via a weighted initial condition. This new block fast transversal filters (BFTF) algorithm is a numerically stable algorithm and can also be used to perform efficient least-squares system identification on any one data block, in which case it shows a moderate computational advantage over the previous most-efficient single-data-block algorithms of Morf et al. (1977), of Marple (1981), and of Kalouptsidis, Manolakis, and Carayannis (1984-1985). Mechanisms for tracking and varying block length from block to block are also presented and evaluated. Finally, we indicate how the new algorithm could be pipelined for maximum throughput with delay proportional to the number of parameters, after computation of the sample correlation lags.

Self-adaptive hybrid data transmission

Abstract: The invention relates to data transmission, especially between a satellite and land-mobile terminals, which is self-adaptive and hybrid, i.e. a system which encodes data in sets of blocks including redundant symbols and redundant blocks, and provides automatic retransmission of lost data blocks and in parallel, correction of detected errors within received blocks. In the embodiment described, the data is encoded in a Reed-Solomon code in a two-dimensional mode. Each set of data is transmitted automatically and continuously; the receiver registers the data received and corrects detected errors in the relevant block up to a threshold number; if the number of detected errors in the block exceeds the threshold, the block is erased. When sufficient data has been received to decode the complete set of blocks, the receiver transmits a reception acknowledgement signal repeatedly. When the transmitter receives the reception acknowledgement signal, it interrupts transmission of the current set and starts transmitting the next set, on reception of which the receiver halts transmission of the reception acknowledgement signal.

Image reduction method

Abstract: A binary image is reduced in size by a method including the steps of: storing the image in bit sequence; dividing the image into transposable blocks; transposing by look up table, for each block having any nonzero data, each group of 6 bits along a first axis to a group of 5 bits; transposing by look up table, for each block having any nonzero data, each group of 6 bits along a second axis to a group of 5 bits; storing said transposed blocks.

Two-dimensional block processors - Structures and implementations

Abstract: Two-dimensional (2-D) block processing technique for linear filtering of digital images is introduced. New 2-D block structures are derived for 2-D recursive digital filters realized by difference equations and state-space formulations. Several special cases have also been considered and the relevant 2-D block structures are given. The computational costs of different implementation techniques employing high-speed convolution algorithms such as fast Fourier transform, number theoretic transform and polynomial transform have been studied. A comparison among the relative efficiencies of these implementation schemes is made and a suitable method is then proposed using short convolution algorithm which results in a minimized computational time.

Personal computer apparatus for block transfer of bit-mapped image data

Abstract: A computer that provides data to a video display using a bitmap display memory organization and bitplane addressing. Separate control is provided for two bitplane backgrounds and for eight reusable and easily movable sprites. Additional logic allows for dynamically-controllable interobject priority and collision detection among data in each of the bitplane backgrounds and sprites. A coprocessor provides for video beam-synchronized changes to data in registers, freeing the main processor for general purpose computing tasks. A block image transfer is provided to rapidly copy data in large blocks from one memory location to another. In hold-and-modify mode, color output circuitry holds the value for a previously displayed pixel while bitplane data modifies those values, allowing for simultaneous display of a greatly increased number of colors.

Performance of Error-Correcting Codes on Channels with Memory

Abstract: Most magnetic recording and many other digital communication channels exhibit statistical dependencies among errors. The design of error-control schemes for such channels .requires proper models and tools that can be used to evaluate error performance after decoding. In this paper a simplified partitioned model of a channel with memory suggested by B. D. Fritchman is considered. This model is used to derive expressions for block and bit error probability bounds for major block burst-error-correcting codes: interleaved, single burst-correcting, and nonbiuary codes. The model-based bounds are compared to the experimental ones using the data obtained for helical scan magnetic tape recorders. The comparison showed an agreement between experimental and analytical data within one order of magnitude, with the average difference being as small as 16 percent in some cases. A simple and effective implementation of a multiple burst-error-correcting scheme based on the majority-logic decoding of interleaved binary codes is suggested. The scheme requires about ten off-the-shelf IC's for both encoder and decoder with the interleaving degree up to 512.

Static Blocking at Railyards: Sorting Implications and Track Requirements

Abstract: In this paper, various strategies for minimizing the amount of switching done at a classification yard are examined. We investigate how the allocation of blocks (the sorting classes recognized at the yard) to classification tracks affects switching work. Given are the sorting classes, as well as the schedule and block makeup of the departing trains. Only static strategies are considered—strategies where every block has been assigned permanently to a classification track. Simple formulas are given for the minimum number of tracks needed to implement a strategy, and for the amount of switching work given a number of tracks. The total track length is also examined. The results are significantly influenced by the number of blocks recognized by the yard; given this number, the results are nearly independent of the train departure schedule, the number of departing trains, and the number of blocks of individual trains. This feature simplifies the study of larger problems (e.g., dynamic blocking strategies) and, ...

Data communication system with block synchronization data in mobile radio

Abstract: A block synchronization data communication system enables data communication to be properly effected even through a transmission channel under an extremely unfavorable conditions as in mobile radio such as automobiles. The block synchronization data communicating system comprises the steps of encoding data to be transmitted and blocking the encoded data, adding a block synchronization signal having a plurality of different successive pattern positioned in the prescribed order to the head of said block data, transmitting the block data added with said block synchronizing signal, receiving said transmitted data and recognizing one of said patterns constituting the block synchronizing signal, estimating the data position based on a block synchronization signal constitution position of the properly recognized pattern, and decoding the block data beginning from said estimated position as received data.

Architecture for block processing computer system

Abstract: A block processing computing system includes a decomposition unit, a control circuit, a system memory, a data block path and a block processor. The decomposition unit receives externally-supplied primitive command packets and decomposes the primitive into machine language operations on computational blocks of data. The control circuitry generates control and address signals for performing the machine level operations. The data block path includes alignment circuitry for selecting data from burst-accessed blocks of data and a macropipeline for controllably storing and transferring blocks of data to and from the block processor. The block processor has interchangeable, double-buffered local zone memories and a parallel set of pipelined vector processors for performing block operations on computational blocks of data.

Relative Efficiency of Two Randomized Block Designs Having Different Plot Sizes and Numbers of Replications and of Plots per Block1

Abstract: Equations for estimating relative efficiency of two randomized block designs having different numbers of replications, plot sizes, and numbers of plots per block are presented. The purpose is to use information of past experiments to improve the proposed design either through increasing the number of replications, or plot size, or both. A decision rule is presented, based on the soil heterogeneity index, b when b 0.7, increase the plot size; when b is between 0.2 and 0.7, changes in both numbers of replications and plot size will be effective. To simpliy the case, 0.2 < b < 0.7, two tables are presented: one shows the relative variance for various plot sizes, and the other shows the ratio of required number of replications and experimental area to obtain a desired relative efficiency. By judicious use of these two tables, the optimum combination of replicate number and plot size can be obtained. Examples are given to demonstrate how the basic equations can be used to answer specific design questions such as: can the efficiency be improved while using the same experimental area, and how can a design be obtained with the same relative efficiency and with no restriction on area.

Disk drive with improved error correction code

Abstract: A rotating disk data storage subsystem is disclosed for recording and retrieving data in blocks of predetermined finite length, each block of data including an error correction code syndrome portion calculated in accordance with a predetermined Galois field error correction algorithm. The subsystem includes a data controller including a unitary, cyclic error correction code syndrome generator/decoder for processing each incoming byte of the block in accordance with the said error correction algorithm in a manner which tests for the presence of any errors and which generates error values from which the errors may be located and corrected. A microprocessor controller has access to the data controller for testing to determine if the generator has determined the presence of an error for an incoming block, and if so, for obtaining the error values. The microprocessor is programmed to process the error values to determine the location and nature of at least one error, and having access to the buffer memory whereby a data byte of the block including an error may be removed and a corrected byte substituted in its place.

Image data converter

Abstract: An image data converter for editing or displaying image data without a large bit image memory for storing bit image data of an entire image. The editing or display is performed in such a way that an inputted image data is compression-encoded in its plurality of blocks in the sub-scanning direction, the counted compressed data length of each block is stored, and thereafter a necessary block is scaled only in its predetermined area at a high speed to a predetermined scale.

Buffer memory control system

Abstract: A buffer memory control system for executing an immediate instruction, including a block fetch control unit for generating a first move-in complete signal indicating that the move-in of the heading subblock from a main memory to the buffer memory is completed. In response to the first move-in complete signal, the fetch and store operation starts without waiting for the completion of the move-in of a full block.

High-speed switching processor for a burst-switching communications system

Abstract: This invention provides a high-speed switching processor which may be employed as a component of a link switch or a hub switch in a burst-switching communications system. When so employed, transmission speeds for integrated voice and data services over communications links between switches may be equivalent to the T1 rate or higher. A burst is a plurality of bytes which represents, for example, a block of data or a spurt of voice energy sensed by silence/voice detectors located at voice ports. In a preferred embodiment, the architecture of the switching processor includes a data/address bus, control including a stored program in a 64-bit wide PROM, a finite-state machine having character and channel states for generating a jump address in the stored program based on the status of an incoming burst, interfaces with other components of the switch such as the queue sequencer, a companion processor, and a dual-port RAM for generating a buffer address as a function of channel number for the dynamic buffer in character memory in which the incoming burst is being stored. In this architecture, most components of the switching processor operate substantially in parallel with and independently of the control which is a contributing factor to the overall speed advantage realized by the switching processor. With software or firmware variations, the switching processor may be employed as several different components of a link or hub switch.

Analysis of the F-16 Flow Field by a Block Grid Euler Approach,

Abstract: : A grid generation procedure has been developed to create complex block grid systems, beginning with the generation of block surfaces, up to the generation of the full block volume grids Parallel to this, a multiple block Euler equation solver has been developed using a hybrid flux vector split and split MacCormack scheme, written to allow very general boundary conditions specification The two codes are utilized herein to generate an inviscid analysis of an entire F-16 transonic flowfield Preliminary results are presented and are seen to compare well with experimental data Even better correlation with experimental data is expected once a fully converged solution is obtained

System and method for encoding and storing digital information on magnetic tape

Abstract: The specification discloses a system and method for storing digital information on a magnetic tape wherein redundant information is generated and also stored so that subsequently unreadable portions of the tape can be regenerated based on the readable portions. The tape is formatted to include a plurality of sequentially arranged blocks, each including a plurality of generally identical data sectors and error-correction sectors. The placement of the data sectors and the associated error-correction sectors within a common block facilitates, and increases the speed of, tape writes and reads. Preferably, a Reed-Solomon code is utilized to generate the redundant information in the error-correction sectors as a preferred balance between recoverability, tape overhead, and speed of encoding.

A method for decoding data transmitted along a data channel, and an apparatus for executing the method

Abstract: Method of decoding data making it possible to correct certain errors, e.g. in synchronization and transmission. The method relates to decoding data transmitted in groups of blocks. Each block has n1+n2 bits, where n1 is the length of a corresponding information word. The information word is extended to an error protection block of n1+n2 bits by application of a linear error protection code and an off-set which indicates the position of the block within a group. Synchronization is established by incremental generation of a position-indicating syndrome from the block. If error correction is found to be necessary, it begins after synchronization. Synchronization is restarted if too many errors occur. A device for implementing the method includes a radio receiver (21), a microprocessor (22) for its control and a universal decoder (11) consisting on the one hand of a demodulation (13) and clock regeneration (12) component, the input of which is connected to the multiplex output of the radio receiver (21) and, on the other, of a broadcast data processing microprocessor (14), the output of which is connected to said microprocessor (22) for controlling the radio receiver.

Video disk recorder and playback unit

Abstract: An optical video disk, an optical disk recorder, and a playback unit for an optical video disk in which a digital data signal is divided into blocks, each being formed of a fixed number of bits, and the length thereof after interleaving is made longer than one field of a television video signal but shorter than one frame thereof. As a result, at least one block is made to correspond to one frame or field of the video signal, and the end portion of the block after interleaving is recorded at a position close to a point corresponding to the vertical synchronizing signal of the video signal and at the same time recorded on a corresponding frame or field basis. Accordingly, digital data in the form of blocks may be made to correspond to specific frames or fields, whereby desired picture images or digital data can readily be retrieved and played back.

Implementation of high-order direct- form digital filter structures

Abstract: High-order direct form structures are generally avoided in the design of digital filters because of a number of finite wordlength problems associated with these structures. However, in adaptive or timevarying filter designs the high-order direct-form structure is a natural and convenient choice. A block floating-point implementation of a high-order direct-form structure is proposed, which gives lower roundoff noise and has improved scaling properties compared to the conventional high-order implementations.