Showing papers on "Carry flag published in 2002"

Data storage system having atomic memory operation

Abstract: A method and system for enabling a director to perform an atomic read-modify-write operation on plural bit read data stored in a selected one of a plurality of memory locations. The method includes providing a plurality of successive full adders, each one of the full adders being associated with a corresponding one of the bits of the plural bit read data. Each one of the full adders has a summation output, a carry bit input and a carry bit output. The method includes adding in each one of the full adders: (a) a corresponding bit of plural bit input data provided by the director; (b) the corresponding one of the bits of the plural bit read data; and, (c) a carry bit fed the carry bit input from a preceding full adder. Each one of the full adders provides: (a) a carry bit on the carry output thereof representative of the most significant bit produced by the full adder; and, (b) a bit on the summation output representative of a least significant bit produced by the full adder. The bit on the summation output is stored in a corresponding bit location in the selected one of a plurality of memory locations. The method selectively couples, or inhibits coupling, the carry bit produced from one of the full adders to the carry bit input of a next successive full adder selectively in accordance with a corresponding bit of a plural bit carry bit mask provided by the director providing a full adder for each one of the bits of the plural bit read stored. The full adder has a carry bit input and a carry bit output. The method includes adding each one of a bits of plural bit input data provided by the director with a corresponding one of the bits of the plural bit read data in the provided full adder together with a carry bit fed the carry bit input of such provided full adder. The full adder provides: a carry output bit; and, a summation of the bits fed to such provided full adder to the corresponding bit location in the selected one of a plurality of memory locations. The method selectively couples, or inhibits coupling, a carry bit produced by one full adder provided for a lower order bit of the plural bit read data to the carry bit input of a second full adder provided by for next, successive higher order bit of the plural bit read data selectively in accordance with one of a plurality of bits of a carry bit mask provided by the director.

4:2 compressor circuit for use in an arithmetic unit

Abstract: A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first intermediate signal indicative of the XNOR of a first pair of the input signals and a second intermediate signal indicative of the XNOR of a second pair of the input signals. The second stage configured to receive at least a portion of the signals generated by the first stage. The second stage generates first and second control signals where the first control signal is indicative of the XNOR of the four input signals and the second control signal is the logical complement of the first signal. The carry circuit is configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal. The sum circuit is configured to receive at least one of the control signals and further configured to generate a sum bit based at least in part on the state of the received control signal. At least one of the first stage, second stage, sum circuit, and carry circuit include at least one CMOS transmission gate comprised of an n-channel transistor and a p-channel transistor having their source/drain terminals connected in parallel, wherein the p-channel transistor gate is driven by the logical complement of the n-channel transistor gate. In one embodiment, the first stage, second stage, carry circuit, and sum circuit are comprised primarily of such transmission gates to the exclusion of conventional CMOS complementary passgate logic.

Logic circuit for fast carry/borrow

Abstract: Each binary carry logic circuit 20 of half adder circuits other than that for the least significant digit comprises a transfer gate 212 turned on when an input bit A 2 is active and receiving a carry-in bit *C 2 at its data input, and a transistor 23, turned on when the input bit A 2 is inactive, connected between a power supply potential VDD and the data output of the transfer gate 212 a signal on which is a carry-out bit *C 3. Transfer gates 212 to 214 of binary carry logic circuits other than that for the least significant digit are connected in chain, and are simultaneously on/off controlled by input bits A 2 to A 4, letting the carry-in bit *C 2 from the least significant digit propagate through the transfer gate chain at a high speed.

Skipped carry incrementer for FFT address generation

Abstract: A method and apparatus are used to generate FFT data addresses for a butterfly stage based upon a computation stage value. The method includes setting a selected bit of a binary word at a logical value, performing an addition operation by adding a logical “1” to the binary word, and skipping a carry bit as selected by a one-hot decoded stage value during the addition operation. The apparatus includes consecutive adders configured to store a binary value and perform an addition operation on the binary value, multiplexers configured to select either the carry out output of the current consecutive half adder or the carry out output of the previous consecutive half adder as the carry in input of a next consecutive adder, and sets of logic gates that provide one bit of the data address.

Timer scheduling method

Abstract: The invention relates to a method for dispatching time clock. Time length of overtime of timer is split according to mathematic carry bit system, for example, if binary system is adopted, the time length is split into the form with 2 raised to the Kth power being accumulated. Chain table of timer category is classified according to the selected carry bit system. The operational steps are as follows: most significant bit of time length of overtime of timer is determined, and the said timer is registered in the tail part of chain table with relevant category. When time length is split in the chain table, if the timer is met, the timer is taken out. Continuous to do so for remainder time length is till to overtime of timer, then overtime job of the timer is started, and the said timer is deleted.

Radio-controlled watch

Abstract: PROBLEM TO BE SOLVED: To provide a radio-controlled watch capable of informing receiving state without directly detecting receiving magnitude SOLUTION: A pulse quality output part 5 detects the existence of an error generation signal with one second interval from on-the-minute information obtained from a time code judging part 3 If there is an error generation signal, it gives '0', and if there is no error generation signal, it gives '1' to a carry flag (CY) 6 The information '1' or '0' received by the carry flag (CY) 6 is shifted in a register 7 A counting part 8 counts the number of '1' existing in the register 7 each second and gives the numerical information to a microcomputer 10 The microcomputer 10 gives an indication data as a letter indication, corresponding to the numerical information to a display 11 The display 11 consists of a liquid crystal panel, for example, and indicates with figure '4', based on the indication data

Associative processor addition and subtraction

Abstract: Methods of adding and subtracting sets of binary numbers using an associative processor. The inner loop over corresponding bits of the operands is executed in only three machine cycles. Only the carry bit of each loop iteration is carried forward to the next loop iteration. At most five logical operations are used per loop iteration for addition, and at most seven logical operations, of which at most five are binary logical operations, are used per loop iteration for subtraction. In each loop iteration, the second input bit is a direct or indirect argument of at most three logical operations in addition, and of at most four logical operations in subtraction. Each loop iteration includes at least one OR operation and at most two XOR operations.

Logical operation circuit

Abstract: PROBLEM TO BE SOLVED: To reduce the limits of clock periods and the number of bits due to operation time of a carry bit of higher digits. SOLUTION: In a logical operation circuit, a first operation section 30 operates is an address operation circuit to operate, for example, X address and a second operation section 40 is an address operation circuit to operate, for example, Y address. When executing logical operations of (2 by n) bits with a linkage between those operations, for example, if X address is set as the higher digits, in the first operation section 30, a carry operation unit 304 operates the carry bit in advance with accepting direct inputted values to provide the carry bit to the operation section 40. Thereafter, in the first operation section 30, a logical operation unit 302 executes logical operations of the inputted values XA, XB held in flip-flops 306, 308. In the second operation section 40, a logical operation unit 402 operates inputted values YA, YB held in flip- flops 406, 408 together with the carry bit from the first operation section 30.

Finding a significant bit in a computer data word

Abstract: The most or least significant bit of a datum can bet determined using parallel operations. This may result in faster location of the most or least significant bit without necessarily introducing more overhead in some embodiments.

Modulo arithmetic overflow control for viterbi decoder

Abstract: A method and apparatus for controlling overflow in Viterbi decoder is disclosed. The present invention allows the metrics to use short words, and to grow freely, by the use of natural wrap-back when overflow occurs. The metric compare process monitors the occurrence of wrap-back and produces results accordingly. In accordance with one aspect of the invention, a “partial subtractions” is used for the compare processes by checking the most-significant bit of each “partial subtraction” result, instead of the carry bit, to determine the comparison result. Based on the comparison result, the metric will be selected, or updated, at the next stage.

Carry lookahead adder for different data types

Abstract: An adder is proposed which has circuitry for calculating the sum of or difference between pairs of unpacked binary numbers having 2 bits or packed binary numbers having 2 bits where m sub-adders, with each sub-adder partition including a plurality of columns and a plurality of rows of cells. The columns of cells each have an input cell in the lowermost row for receiving bits of each of the pairs of numbers. Each sub-adder above the lowest significance sub-adder has a lowest significance column input cell arranged to receive a third input bit. The cells in the remaining rows of the or each sub-adder above the lowest significance sub-adder are arranged to prevent the carry-over of a carry bit from the most significant column of the preceding sub-adder being introduced into the sub-adder, depending on whether the third input bit is zero or one.

Carry-save multiplier

Abstract: The invention relates to a carry-save multiplier for encoded data, comprising a first operand register (10), a second operand register (12), a multiplication intermediate-result register (14), in addition to a plurality of one-bit full adders (160, 161, 162, ...) of the order (0) to the order (n-1). According to the invention, each one/bit full adder calculates an encoded carry bit for the order (i) and an encoded sum bit for the order (i) from an encoded bit of the order (i) of the second operand, an encoded carry bit of the order (i) from the multiplication intermediate-result register (14) and from the encoded sum bit of the next-highest order (i+1) from the multiplication intermediate-result register (14) and stores said bits in the multiplication intermediate-result register (14). To maintain the same coding base for each order, the multiplier is provided with a code conversion device (20i), which calculates a code conversion key from a combination of the encoding parameters (ki) and (ki+1) of the relevant positions and feeds said key to the corresponding one-bit full adder (16i). The carry-save multiplier for encoded data stores all the bits in the registers in encoded form and preferably comprises a one-bit full adder, which calculates encoded output data directly from encoded input data. The carry-save multiplier therefore does not generate plain text at any stage and is thus secure against direct or indirect attacks.