Showing papers on "Carry-lookahead adder published in 2001"

The circuit design of multiple-valued logic voltage-mode adders

Abstract: Novel quaternary half adder, full adder, and a carry-lookahead adder are introduced. The proposed circuits are static and operate in voltage-mode. Moreover, there is no current flow in steady states, and thus no static power dissipation. Although the comparison in transistor count shows that the proposed quaternary circuits are larger than two respective binary ones, benefits in parallel addition arise from the use of multiple-valued logic. Firstly, the ripple-carry additions are faster because the number of carries are half compared to binary ones and the delay from the input carry through the output carry is relatively small. Secondly, the carry-lookahead scheme exhibits less complexity, which leads to overall reduction in transistor count for addition with a large number of bits.

A fast hybrid carry-lookahead/carry-select adder design

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Application of logical effort on delay analysis of 64-bit static carry-lookahead adder

Abstract: This paper presents the transistor-level analysis of the 64-bit static carry-lookahead adder (CLA). The carry blocks were implemented in two schemes: (A) 2-level and (B) multilevel. The logical effort technique was used to optimize the circuits for best performance. The analysis was verified with SPICE simulation, using 0.18 /spl mu/m, 1.8 V CMOS technology, and confirmed with small error. In addition, scheme B showed 12% improvement due to faster gate in carry block and less loading in (P,G) ones.

A 1.25 GHz 32-bit tree-structured carry lookahead adder

Abstract: In this paper, a 32-bit tree-structured carry lookahead adder (CLA) is proposed by using the modified all-N-transistor (ANT) design. The 32-bit CLA not only possesses few transistor count, but also occupies small area size. Moreover, the post-layout simulation results given by TimeMill show that the clock used in this 32-bit CLA can run up to 1.25 GHz. The proposed architecture is also easily expanded for long data additions.

A 1.2 V 500 MHz 32-bit carry-lookahead adder

Abstract: In this paper a 1.2 V 32-bit carry lookahead adder is proposed for high speed, low voltage applications. The proposed new 32-bit adder uses Non-full Voltage Swing True-Single-Phase-Clocking Logic (NSTSPC) to implement the proposed carry lookahead adder. Because the internal node of NSTSPC was non-full swing, its operation speed would be higher than the conventional TSPC. Moreover, the supply voltage for the new adder is 1.2 V, thus the power dissipation would also be reduced. The 32-bit CLA adder using 0.35 /spl mu/m 1P4M CMOS technology with 1.2 V power supply could be operated at a 500 MHz clock frequency.

Phase-mode pipelined parallel multiplier

Abstract: We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices of the phase-mode logic. Experimental operations of the ICF gate and the Adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This structure has a regular layout, hence it is suitable for a pipeline scheme. In the final stage of multiplication, a fast carry lookahead adder is used for generating a multiplication result. Using a Verilog-HDL simulation, we show that the parallel multiplier with 2.5 kA/cm/sup 2/ Nb/AlO/sub x//Nb junctions can operate over 10 GHz.

Designing low-power energy recovery adders based on pass transistor logic

Abstract: The novel design of various adiabatic adders based on pass transistor logic is introduced. Also, a new 1-bit full adder basic cell with a small number of transistors is designed. The architectural design of each adiabatic adder and new formulas for their corresponding delay, are presented. The performance of various adiabatic adders, in this work, against the performance of theirs CMOS counterparts, is discussed. All adders (i.e. conventional CMOS and adiabatic) were simulated by the PowerMill tool for power dissipation, latency and energy efficiency. In addition, a first estimation of area was done by the transistor count. Also all adders were simulated at 3.3 V and 5 V, for a broad range of frequencies. Experimental results indicate that the adiabatic adders outperform the corresponding conventional adders in terms of power consumption, and exhibit a lower hardware complexity.

Multiple block adder using carry increment adder

Abstract: A multiple block adder is provided wherein carry select adder (CSA) is used in the most significant bit (MSB) block, a carry increment adder (CIA) is used in the least significant bit block and a combination of carry increment adder (CIA) and carry lookahead adder (CLA) circuit is used in the middle block.

P hase-Mode P ipelined Parallel Multiplier

Abstract: We propose a pipelined parallel multiplier in phase-mode logic. The multiplier can be composed of combinations of gates which are the basic devices ofthe phase- mode logic. Experimental operations of the ICF gate and the Adder cell for the multiplier are reported. The proposed multiplier has a Wallace-tree structure comprising trees of carry save adders for the addition of partial products. This structure has a regular layout, hence it is suitable for a pipeline scheme. In the final stage of multiplication, a fast carry lookahead adder is used for generating a multiplication result. Using a Verilog-HDL simulation, we show that the parallel multiplier with 2.5kA/cm2 Nb/AlOx/Nb junctions can operate over 10 GHz.