Showing papers on "Circuit diagram published in 1998"

Connectivity-based approach for extracting layout parasitics

Abstract: A layout parasitics extraction system. The layout parasitics extraction system is a connectivity-based approach for extracting layout parasitics. The system creates a connectivity-based database (1104), where geometries of a layout are organized by nets of the circuit schematic. The system allows net-by-net extraction (1124) of layout parasitics using a connectivity-based database. A user can select a net or nets for extraction. The system creates a database containing nets and their extracted layout parasitics (1132). The system can generate a netlist format file from this database to provide for back annotation of layout parasitics into a circuit schematic for further circuit analysis.

JiffyTune: circuit optimization using time-domain sensitivities

Abstract: Automating the transistor and wire-sizing process is an important step toward being able to rapidly design high-performance, custom circuits. This paper presents a circuit optimization tool that automates the tuning task by means of state-of-the-art nonlinear optimization. It makes use of a fast circuit simulator and a general-purpose nonlinear optimization package. It includes minimax and power optimization, simultaneous transistor and wire tuning, general choices of objective functions and constraints, and recovery from nonworking circuits. In addition, the tool makes use of designer-friendly interfaces that automate the specification of the optimization task, the running of the optimizer, and the back-annotation of the results of optimization onto the circuit schematic. Particularly for large circuits, gradient computation is usually the bottleneck in the optimization procedure. In addition to traditional adjoint and direct methods, we use a technique called the adjoint Lagrangian method, which computes all the gradients necessary for one iteration of optimization in a single adjoint analysis. This paper describes the algorithms and the environment in which they are used and presents extensive circuit optimization results. A circuit with 6900 transistors, 4128 tunable transistors, and 60 independent parameters was optimized in about 108 min of CPU time on an IBM RISC/System 6000, model 590.

Method for incorporating noise considerations in automatic circuit optimization

Abstract: A method of incorporating noise considerations during circuit optimization includes the steps of: specifying a circuit schematic to be optimized; specifying at least one noise criterion as a noise measurement, including the signal to be checked for noise, the sub-interval of time of interest, and the maximum allowable noise deviation; providing each noise criterion as either a semi-infinite constraint or a semi-infinite objective function; specifying at least one variable of the optimization; converting the semi-infinite noise constraints and the semi-infinite noise objective functions into time-integral equality constraints; optionally, if required, providing additional optimization criteria other than noise as, for each such criterion, either objective functions or constraints; creating a merit function to be minimized to solve the optimization problem; simulating the circuit in the time-domain; computing the values of the objective functions and constraints; efficiently computing the gradients of the merit function of the optimizer (including contributions of all objective functions and constraints and the time-integrals representing noise considerations) preferably by means of a single adjoint analysis; iteratively providing the constraint values, the objective function values and the gradients of the merit function to a nonlinear optimizer; and continuing the optimization iterations to convergence.

Automated method for adding attributes identified on a schematic diagram to an integrated circuit layout

Abstract: An attribute on a netlist (31) is placed on a layout (33) to allow an automated approach for adding a feature to the layout (33) to be implemented The netlist (31) or schematic diagram of a circuit is simulated on a Computer Aided Design (CAD) tool to verify circuit functionality A layout tool (32) generates the layout (33) of the netlist (31) Adding a feature, for example, an extra implant to a source region of a device requires knowledge of device orientation not included in the layout (33) A Layout Versus Schematic (LVS) program (34) is run with the netlist (31) and the layout (33) Connectivity information from the LVS run is retrieved and placed in a connectivity mapping file (35) A mapping program (36) uses the connectivity mapping file (35) and the layout (33) to generate layers indicating and marking device orientation The layers when added to the layout (33) produce an oriented layout (37) A layer generation program (38) uses the oriented layout (37) and the connectivity mapping file (35) to generate layers required to produce the feature on devices of the oriented layout (37)

Method for supporting the design of semiconductor integrated circuit and system using the same method

Abstract: An overall calculation of a semiconductor integrated circuit comprising an assemblage of a plurality of circuit blocks is predicted at an initial stage of design. When a circuit block is selected by clicking an analysis button on the screen of the system analysis browser, the block is changed to the screen of the circuit block analysis browser for the selected circuit block. When a parameter unique to the circuit is input to the parameter input panel to click the start button, the performance prediction value of the circuit is displayed on the parameter input panel. This is performed for each circuit block. On the data format panel of the system analysis browser screen, the prediction of the wiring delay time between respective circuits is displayed together with the performance prediction value of each circuit block.

Feature-recognition for mems extraction

Abstract: Microelectromechanical systems (MEMS) integrating multidomain sensors and actuators with conventional microelectronic batch fabrication processes are becoming increasingly complex. In order to design systems with large numbers of multi-domain components, we need to use a hierarchical structured design approach, with design at the schematic level instead of the traditional layout representation used in MEMS design. However, since fabrication can only be done from a layout representation, an automatic or manual layout generation from schematic is necessary. It is essential to be able to translate from the layout representation back to the schematic to reason about layout correctness in meeting the schematic’s function as well as to extract geometric parameters for functional simulation. An extraction module is developed which reads in the geometric description of the layout structure and reconstructs the corresponding schematic. This schematic can then be fed to an ordinary differential equation solver or can be compared with the design schematic to validate the correctness of the designed layout. The extraction module also minimizes the number of nodes required to represent the schematic as a netlist. The results presented show the success of the module for some example MEMS designs.

Decision tree forming method for error localisation in technical system

Abstract: The method involves using a computer to produce a decision tree (12) for localizing an error of a technical system. Circuit diagram data (3) are produced by the computer from a circuit diagram (1) of the system. Data (11) which represent the decision tree are produced by the computer from the circuit diagram data and from predetermined knowledge data (5) regarding predetermined errors. The knowledge data are preferably derived from known errors (6) or from the produced decision tree.

Power supply circuit diagram design system

Abstract: A data library, a CPU and a memory store a design aid program which designs power supply circuit diagrams based on the data library in accordance with given conditions for a power supply circuit. Therefore, design errors associated with an increased design scale are prevented and the design time is shortened. The given conditions are taken as the respective vertical and horizontal intervals between power portions having first pins for connecting to a power supply and second pins for connecting to earth, and the number of rows and the number of steps of the power portions. Then, multiple available power portions are arranged according to the given conditions by a design aid program and the multiple arranged power portions are wired to a power supply symbol and an earth symbol, respectively.

Time-domain circuit modeller

Abstract: A method of, and apparatus for, obtaining a representation of an electrical circuit (400) suitable for time-domain simulation. The electrical circuit comprises a physical structure (102), which is modelled using electromagnetic field analysis, and also comprises a remainder circuit (104) of circuit components which are interconnected with the physical structure. The electromagnetic field analysis is capable of generating at least a high-frequency equivalent circuit which is representative of the physical structure (102) and is valid at the operating frequency of the circuit but not at DC. The method comprises including a set of DC sources (E1 to Ek) to ensure that, in a time-domain simulation, improved DC bias conditions are provided for any non-linear components in the remainder circuit. The DC sources may be voltage sources in each interconnection, current sources between each interconnection and a zero voltage reference interconnection, or a combination of the two.

ECIR-an electronic circuit diagram image recognizer

Abstract: This paper describes a technique developed to analyze and recognize paper based electronic circuit diagram images. One of the key aspects of this recognition system relies on the identification of feature points used to guide a new line vectorization method developed for circuit diagram images. The feature paints are also used as a discriminate element in the symbol classification process. Once the lines are vectorized, the open symbols are first identified by a syntax-based classifier, followed by the identification of the loop-based symbols using a supervised parametric statistical classifier. We have demonstrated the proposed system by implementing and testing it on various real images of circuit diagrams.

Ladder programming device and its method

Abstract: PROBLEM TO BE SOLVED: To improve the work efficiency of the generation of a ladder circuit diagram and to reduce a bug generation rate in a ladder program by calling a partial ladder circuit diagram which is temporarily stored in a storage part and copying it in the ladder circuit diagram. SOLUTION: A ladder circuit diagram generation part 2a arranges a ladder parts diagram on a ladder circuit generation screen displayed by a display part 1 based on a prescribed procedure and generates a ladder circuit diagram. A partial ladder circuit diagram storage part 4a adds a partial ladder circuit number to a partial ladder circuit diagram designated by a designation part 2b and temporarily stores it. A copying part 2c instructs a partial ladder circuit number, calls the partial ladder circuit diagram which is temporarily stored in the partial ladder circuit storage part 4a and copies it in the ladder circuit diagram in the middle of generation. An address setting part 2d sets an address in the arranged ladder parts diagram. A ladder program generation part 2e generates a ladder program based on the ladder circuit diagram which is address-set. COPYRIGHT: (C)2000,JPO

Verification device for lsi design

Abstract: PROBLEM TO BE SOLVED: To provide a verification device for LSI design capable of detecting wiring for which an allowable current value becomes a violation in a minimum wiring width from a circuit simulated result and preventing an allowable current capacity error on layout pattern design. SOLUTION: The verification device for the LSI design for verifying a current capacity value is provided with a means 7 for calculating the allowable current value of the minimum wiring width and detecting a device terminal exceeding the allowable current value and the means 8 for comparing and verifying a circuit diagram and the connection information of a layout pattern and emphasis-displaying the wiring on a layout diagram connected to the terminal detected by the means 7 for detecting the device terminal exceeding the allowable current value.

FP 14.7: A Fully Integrated 2.7V 0.35pm CMOS VCO for

Abstract: Figure 2 presents the circuit diagram. M1 and M2 (each 143.4pd0.36~m) form the differential negative resistor; they are biased with 2mA at a VGST of only about 140mV. The varactor diodes D1 and D2 are PMOS p++ source/drain diffusions in the nwell. Their layout and wiring are optimized for maximum quality factor. Figure 1 shows the measured quality factor of a varactor test structure. A quality of 5 to 6 is available in the 45GHz region. A buffer (M3 and M4 each 72.1pd0.4pm) is included to drive the off-chip loads. In a fully-integrated wireless application the VCO needs to drive only smaller on-chip loads. The buffer transistors are therefore biased from a 3.3V supply to obtain the necessary driving capability from reasonably sized buffer devices. The current bias transistor M5 (247.2yd0.4pm) is connected at the center tap of the inductor and does not load the tank. The parasitics of M1 and M2 represent 67% of the total tank capacitor. The parasitics of M3 and M4 contribute 15% and the fixed part of the varactor capacitance contributes 18%. The calculated quality factor of the tank capacitor is about 8.5.

Semiconductor integrated circuit and test method therefor

Abstract: A reconfigurable circuit is reconstructed to three or more operating circuit blocks. Upon testing, the same data is inputted to each of the reconstructed operating circuit blocks. A majority circuit formed in the reconfigurable circuit compares results of operations of the operating circuit blocks and outputs information indicating which of the operating circuit blocks is in trouble.

Collating device and recording medium

Abstract: PROBLEM TO BE SOLVED: To provide a collating device which performs the automatic collation among a circuit diagram, a substrate diagram and a parts list to show a mismatching part and at the same time performs the second collation in response to the correction input for correction of the mismatching part by extracting the necessary information on the circuit diagram, the substrate diagram and the parts list to collate them with each other for a collating object that is set on a collation mask. SOLUTION: A 3-point collation means 4 extracts the necessary information on a circuit diagram, a substrate diagram and a parts list and collates them with each other based on a collation rule 8 for a collating object that is registered on a collation mask 7 in regard to a range relation to a node that is designated with display of a device type tree. A result display means 5 shows the 3-point collation result of the means 4, and a correction means 6 performs again the 3-point collation and displays this collation result when the 3-point collation result is shown by the means 5 and the node that is displayed with emphasis of the mismatching and corrected. That is, it's possible to display the mismatching in a list and to correct it by checking the 3-point collation.

Circuit diagram designing method considering specification, circuit information preparing method and cad system

Abstract: PROBLEM TO BE SOLVED: To provide a circuit diagram designing method, circuit information preparing method and CAD system with which circuit information corresponding to plural machine types can be unified and managed unitarily on one circuit diagram. SOLUTION: A master circuit diagram including all machine types of circuit diagram information is prepared, the circuit areas of parts information made different by machine types are set into that master circuit diagram as partial circuit areas, the parts information by machine types corresponding to each machine type in the partial circuit areas is set and managed as a table and further, the circuit information corresponding to each arbitrary machine type is extracted and prepared. Besides, when extracting the circuit information of any arbitrary machine type, the connecting state of signal lines connected to unwanted parts is traced and retrieved to the branching point of signal lines or the terminal of other parts and unwanted signal lines are deleted.

Redesignability analysis of digital VLSI circuits with incomplete implementation information

Abstract: This paper describes a new problem of digital circuit design-redesign of digital VLSI circuits with incomplete implementation information-and presents a solution-redesign process. Efficient algorithms are developed to derive the transfer functions of the portion with incomplete implementation information. Thus, the portion can be reimplemented using the derived transfer functions. We do not intend to discover the exact circuit schematic and components that were present in the circuit originally implemented. Rather, the functions originally intended to be present will be identical. A set of simple rules is proposed in this study to quickly analyze the redesignability of a target circuit.

Integrated circuit layout designing circuit

Abstract: PROBLEM TO BE SOLVED: To provide an integrated circuit layout designing circuit which enables an integrated circuit to be improved in capacity, lessened in cost and design manhours, and enhanced in design quality. SOLUTION: A scan chain retrieval means 3 retrievers scan chain net data from circuit diagram data where a minimum delay composition circuit is not present after a logic design is made, and the scan chain net data are stored in a scan chain net data storage means 4. A scan chain line length computing means 7b executes processing such as logic verification, delay analysis, and layout, then retrieves a target flip flop from the scan chain net data, and then calculates the line length of each scan chain. A scan chain minimum compensation circuit calculation means 7c selects a delay circuit which is to be inserted basing on the minimum delay compensation parameters of a minimum compensation parameter storage means 8 and the line length of the scan chains. A minimum delay compensation circuit insertion means 7d adds the selected delay circuit to the circuit diagram data and arranges it.

Simulation device for lsi designing circuit

Abstract: PROBLEM TO BE SOLVED: To perform the circuit simulation in a short time and in consideration of a parasitic element by calculating virtually the parasitic element information from only the circuit information and the layout pattern area. SOLUTION: A circuit information input means 1 inputs the circuit information to undergo the circuit simulation. A virtual wiring area calculation part 7 calculates the total area of wiring areas from the virtual area of a layout pattern given from a designer and the sum total of of layout pattern areas of the semiconductor devices. A wiring parasitic element information calculation part 9 calculates the parasitic resistance value and the parasitic capacity value of every wiring based on the prepared parasitic resistance and capacity coefficients. Then a wiring parasitic element information output part 11 adds the parasitic element information on every wiring to the circuit information and holds this circuit information at a parasitic element information added circuit information holding part 12. The parasitic element information is shown on a circuit diagram via a display part 13.

Semiconductor circuit extracting apparatus

Abstract: PROBLEM TO BE SOLVED: To enable circuit extraction in a condition close to the actual circuit considering the influence of capacitive coupling between internal wiring of a cell and peripheral and upper layer wiring of the cell, in a semiconductor circuit extraction apparatus for extracting a circuit diagram from a layout diagram of the cell. SOLUTION: Original cell layout data 3 are read into virtual wiring adding means 1, and modified cell layout data 4 are produced by adding a virtual wiring layout to the upper layer or periphery of a layout of a cell. As a result, capacitive coupling is provided between the internal wiring of the cell and the virtual wiring. A net list 5 is produced from a circuit extracting means 2 by extracting the circuit including the above-mentioned coupling capacitance based on the modified cell layout data 4.

Efficient high-speed CMOS design by layout based schematic method

Abstract: As the diffusion area and the wire capacitance worsen the circuit performance in very high speed CMOS design, the results between schematic and layout differ from each other because of missing parasitic components in the schematic. We address a layout based schematic (LBS) method for high speed CMOS cell design. In our method, we introduce different types of MOS transistors and a wire capacitance estimation method, based on layout knowledge. The simulation results at very high speed show that the difference between LBS and real circuit layout is much smaller, less than 3 percent in rise time, compared to the difference in the worst case up to 65 percent in original schematic. The result of LBS is reliable and easy to be optimized during the schematic procedure. It will reduce the design time and cost in high speed circuit design. We also believe that the LBS is more convenient to be translated into the real layout than the original schematic.

Manufacture of electrical wire for wiring

Abstract: PROBLEM TO BE SOLVED: To reduce wiring work man-hour and to eliminate wiring errors by combining wiring diagram data and wiring route diagram data, calculating an electrical wire length, preparing automatic terminal processing data and fully automatically performing a terminal processing. SOLUTION: An extension connection diagram 13 is prepared from circuit diagram data 12 for indicating a connection state among respective equipments packaged to a distribution panel and a control panel, etc., the external shape and arrangement of the respective equipments are inputted based on the connection diagram 13 and an external shape diagram/arrangement diagram 23 is prepared. Then, based on the diagrams 13 and 23, a wiring diagram 33 is prepared from the wiring diagram data 32 including the terminal information of a connection destination or the like. Further, the wiring route diagram data 42 are prepared by using a wiring route/connection part definition means 41. Also, terminal processing specifications are inputted for respective electrical wires based on the wiring diagram 33 and terminal processing source data 52 are prepared. Then, the shortest electrical wire length on respective wiring routes is calculated by using the data 32, 42 and 52. Further, the automatic terminal processing data of a list form along with the obtained electrical wire length are prepared and the electrical wires 100 for wiring in the respective kinds of the specifications are manufactured in a processor 90.

Designing method for semiconductor integrated circuit

Abstract: PROBLEM TO BE SOLVED: To improve the workability, to facilitate the design, to make the design efficient, and also to reduce the design time by expanding and displaying a hierarchical structure in a tree shape with cell names and/or instance names and displaying the circuit diagram data of a designated cell name or instance name on a screen to perform circuit design. SOLUTION: When a designing device is started, the cell name 'TOPSCH' in the highest order in the hierarchical structure of a circuit is displayed on a screen. And, when the commands 1 to 9 of a menu are selected, hierarchical data are opened on a memory inside the device and information necessary to a mode designated by the commands 1 to 9 is extracted and shown on the screen. That is, the structure of a lower layer is shown in each hierarchy by selecting the commands 1 to 9 on the menu. Thus, the hierarchical structure of design data of a circuit is shown in a tree shape and also the circuit data can directly be opened from there so that needed circuit data can easily and also quickly be found.

OLYMPO: a GaAs compiler for VLSI design

Abstract: A gallium arsenide automated layout generation system (OLYMPO) for VLSI circuits and system design has been developed. Cell, macrocell and module compilers are the basis of the layout automation tool. The cell and macrocell compiler takes a circuit schematic at logic level and outputs a mask layout. The compiler uses a full-custom layout style, called RN-based cell model. The cell compiler can be used as a cell library builder and it is embedded in a random logic macrocell and an iterative logic array generator for module generation. Experimental results for datapath generation (adders, multipliers, FIR filters, register modules, among others) demonstrate that OLYMPO generates complex and compact layouts and the synthesis process can be interactively used at the system design level.

Direct calculation of scattering parameters of SCN node

Abstract: A schematic diagram of the circuit model of the generalised SCN node is presented. The node circuit is presented as a composition of three topologically equal plane sections. A direct approach to the symbolical evaluation of the scattering parameters is presented. The node can be represented as a combination of multiports which enable wave scattering analysis and direct evaluation of the scattering parameters of the node.

Cryogenic Control System for the g-2 Muon Ring

Abstract: The g-2 Muon storage ring consists of three superconducting solenoids 15 meters in diameter, and a beam Inflector solenoid 1.7 meters in length. All superconducting solenoids are indirectly cooled by forced two-phase helium. Cryogenic cooling is accomplished via a J-T circuit and a LHe control dewar. The control System for this cryogenic system is built around commercially available Programmable Logic Controllers (PLC’s) and cryogenic hardware for monitoring temperature, pressure and flow control. The complexity of this system necessitated the use of a graphical user interface (GUI) which permitted operators to perform monitoring and control functions from a central control room. The graphical interface allowed for rapid operator training and, with the cooling circuit schematic shown graphically they can respond to critical situations promptly. Critical data points on the experiment are logged in the software and historical trends are provided for. Using a software based system allowed for rapid system revisions as they were required. Flow control can be performed manually by the operator or automatically by the software based on linear control algorithms. The system has been in use for two years with successful results.

Circuit diagram display method and device and cad design device

Abstract: PROBLEM TO BE SOLVED: To draw a block diagram in a size accordant with the roughly estimated area value by calculating an area ratio from the circuit information and then calculating the coordinate of a desired drawing from the circuit information and the calculated area ratio for drawing the relevant drawing SOLUTION: A largest port number retrieval means retrieves the largest number of ports from the port list information (S3), and a coordinate calculation means calculates the horizontal and vertical coordinates of the block size based on the largest port number out of all circuit blocks supplied from a buffer (S4, S7) An area ratio calculation means calculates an area ratio based on the horizontal and vertical sizes of the block having the largest number of ports and also on the roughly estimated area ratio of the block having the largest number of ports that is supplied from the buffer (S8) Then a drawing coordinate calculation means calculates the horizontal and vertical coordinates of the block to be drawn based on the area ratio and the roughly estimated area value of the processing block number (S10)

Layout verifying device

Abstract: PROBLEM TO BE SOLVED: To lighten the load of circuit simulation and to speed up layout verification by deleting element symbols for which verification flags are set off from an entire net list and generating a partial net list. SOLUTION: An element extraction part 2 extracts element data 3 including a parasitic element from an entire layout figure 1 and a net list generation part 5 generates a net list 6 for the whole layout. An element name correspondence generation part 8, on the other hand, obtains element name correspondence information 10 from an entire circuit diagram 9 and element data 3 by making element names correspond to respective elements. Further, a verification flag OFF setting part 11 sets verification unnecessary parts OFF among the respective elements in the entire circuit diagram 9 to obtain an OFF-set circuit diagram 12. Then an OFF element deletion part 13 retrieves the elements set OFF in the OFF set circuit diagram 12 from a net list 6 and deletes their element descriptions from the net list 6. Consequently, the partial net list 14 wherein only elements to be verified are described is obtained.

Logic circuit verifying device

Abstract: PROBLEM TO BE SOLVED: To perform verification for time proportional to the change amount of circuit by verifying only a changed circuit section even in case of large scale circuit. SOLUTION: Concerning a logic circuit verifying device with which a whole circuit is provided with plural circuit diagrams and the respective circuit diagrams are equipped with circuit diagram files so as to verify a logic circuit, this device has a memory cell instance name extracting means 1 for reading all the instance names of memory cells provided in the changed circuit diagram file to become the object of verification, inter-memory cell partial circuit extracting means 2 for extracting a partial circuit for generating a signal to be inputted to the input terminal of read memory cell before and after the change, logic verifying means 3 for verifying the coincidence/non-coincidence of logic before and after the change of extracted partial circuit, and non- coincident part diagram display means 4 for displaying the noncoincident part and the input signal at that time.

Logic circuit generating device

Abstract: PROBLEM TO BE SOLVED: To provide a device capable of generating a partial logic circuit diagram only for a partial specified part even when complete description is not obtained at the time of generating a logic circuit diagram based on a file described by hardware description langage (HDL). SOLUTION: At the time of selecting 'partial circuit generating mode' from a keyboard 11, a partial circuit generating part 16 is started by a processing mode discriminating part 12. A statement extracting part 16a in the generating part 16 extracts a specified range statement PF partially specified from the contents of an HDL file 17. A local signal extracting part 16b extracts an input signal and an output signal from the statement PF and generates an intermediate file IF obtained by converting intermediate language. On an assumption that all the extracted input and output signals are external signals, a partial circuit generating part 16c generates a partial logic circuit diagram from the file IF.