Showing papers on "Clock domain crossing published in 1982"

Wired spread spectrum data communication system

Abstract: A wired spread spectrum data communication system includes a modulator and a demodulator coupled to a transmission line having other signals thereon. The modulator includes a pseudo-noise (PN) generator and a clock providing, respectively, a PN code signal and a clock signal for combination in exclusive-OR (XOR) gates with a low bit rate data signal. The demodulator includes a phase locked loop for clock signal recovery and an identical PN generator providing, respectively, a local clock signal and PN code signal for combination in XOR gates with the encoded data signal for the removal of the clock and PN code signal components from the encoded data signal. The demodulator further includes circuitry for synchronizing the local PN code signal with the PN code component of the incoming encoded data signal.

CMOS Circuit with reduced power dissipation and a digital data processor using the same

Abstract: In an information processor employing a CMOS circuit comprising a first inverter constructed of CMOS field effect transistors and performing a dynamic operation in response to clock signals, and a second inverter which receives an output from the first inverter and which is also constructed of CMOS field effect transistors, the supply of clock signals to the first inverter is stopped in response to a particular microinstruction After the supply of clock signals is stopped, the output voltage of the first inverter is clamped to a predetermined value, thus reducing the power dissipation in the dynamic CMOS circuit and also preventing the deterioration of data during the stopping of clock signalsY

Phase-locked loop circuit arrangement

Abstract: The described invention relates to a phase-locked loop circuit arrangement for synchronizing an oscillator to a Non-Return-To-Zero data signal in which a transition from one potential level to another represents a data transition from one binary value to another. A local clock signal is provided by means of a controllable oscillator and a phase comparator compares the phases of the data and clock singals with one another. The frequency of the oscillator is adjusted by means of a control signal in dependence upon an amount by which the phase of the data leads that of the clock signal and vice versa. In any cycle of the clock signal in which the phase of the clock signal leads that of the data and in which no data transition occurs the application of a control signal to the oscillator is inhibited. The invention is particularly applicable to teletext receivers.

Skew-free clock circuit for integrated circuit chip

Abstract: An op-amp feedback arrangement is used to provide non-skewed clock pulses from a source of skewed clock pulses. Any skew in the clock-in pulses results in a change in the average voltage of a clock-out pulse at the output of the arrangement. The average voltage of the clock-out pulse is compared to a reference voltage to produce a control signal which adjusts the average voltage at the output. Critical transitions in the clock pulses occur at precise time relationships under the control of the control signal.

Synchronizing Large Systolic Arrays

Abstract: Parallel computing structures consist of many processors operating simultaneously. If a concurrent structure is regular, as in the case of a systolic array. it may be convenient to think of all processors as operating in lock step. This synchronized view, for example, often makes the definition of the structure and its correctness relatively easy to follow. However, large, totally synchronized systems controlled by central clocks are difficult to implement because of the inevitable problem of clock skews and delays. An alternative means of enforcing necessary synchronization is the use of self-timed, asynchronous schemes, at the cost of increased design complexity and hardware cost. Realizing that different circumstances call for different synchronization methods, this paper provides a spectrum of synchronization models; based on the assumptions made for each model, theoretical lower bounds on clock skew are derived, and appropriate or best-possible synchronization schemes for systolic arrays are proposed. In general, this paper represents a first step towards a systematic study of synchronization problems for large systolic arrays. One set of models is based on assumptions that allow the use of a pipelined clocking scheme, where more than one clock event is propagated at a time. In this case, it is shown that even assuming that physical variations along clock lines can produce skews between wires of the same length, any one-dimensional systolic array can be correctly synchronized by a global pipelined clock while enjoying desirable properties such as modularity, expandability and robustness in the synchronization scheme. This result cannot be extended to two-dimensional arrays, however--the paper shows that under this assumption, it is impossible to run a clock such that the maximum clock skew between two communicating cells will be bounded by a constant as systems grow. For such cases or where pipelined clocking is unworkable, a synchronization scheme incorporating both clocked and "asynchronous" elements is proposed.

Frequency synthesizer and digital phase lock loop

Abstract: In one aspect the invention features a digital synthesizer having clock circuitry to provide a clock pulse train, synthesizer circuitry to provide a synthesized pulse train at a frequency such that multiple clock pulses occur between pairs of successive synthesized pulses, and phase control circuitry to cause an effective shift in the synthesized pulse train frequency by causing, between pairs of successive synthesized pulses, a number of phase shifts in the clock pulse train.

Decentralized generation of synchronized clock control signals having dynamically selectable periods

Abstract: In a microprogrammed processor consisting of several circuitized chips, which are to be synchronously operated, each chip is provided with its own local clock generator or T-ring for deriving therefrom timing signals required during the subphases of micro instruction execution. A master clock connected to all of the T-rings by lines of equal length forces the individual T-rings to operate synchronously and keeps them operating in such a manner. In addition, reset circuitry is provided for forcing all of the T-rings to their first timing interval for initial synchronization thereof or, at an appropriate time, when a micro instruction requiring less than the maximum number of available T-ring timing signals is executed. The timing signals which are locally produced are subject to little delay on their way to the various local switching points. Thus, the entire system can be operated at a higher oscillator or master clock frequency to take advantage of the enhanced processing and transfer speeds of modern, highly integrated circuit chips.

Electronic apparatus having low radio frequency interference from system clock signal

Abstract: A printer having greatly reduced radio frequency interference from the system clock signal therein is provided by angle modulating the system clock signal in accordance with a desired modulation signal. The modulation signal is chosen so as to spread and thereby reduce the energy level of the system clock signal at the carrier and at the harmonics without interfering with proper detection of the system clock signal by the electronic circuits within the printer requiring the clock signal for proper timing. In a first embodiment the angle modulation is provided by an FM modulator responsive to a modulating signal which is either sinusoidal or randomly varying in nature. In a second embodiment the angle modulation is provided by an arrangement which combines a modulated subcarrier with the basic clock frequency in a phase locked loop.

Data tracking clock recovery system using digitally controlled oscillator

Abstract: A clock recovery system including a VCO responsive to a voltage signal for generating a clock signal. A phase detector includes a register and a PROM, the register counting the clock signal to derive the output clock signal. The PROM is responsive to input data and the count in the register to detect and store information concerning relative phase relationships. A counter contains a count from which the control voltage for the VCO is derived. The PROM is operable to alter the count in the counter, thereby performing frequency adjustments, and to alter the count in the register to perform phase adjustments. Also, a converter, operable by the phase detector, may also derive a voltage signal for damping purposes.

Time base corrector

Abstract: A time base corrector for removing time base errors from composite color video signals has a write clock and write start pulse generating circuit for providing write clock and write start pulses in synchronism with horizontal sync signals separated from the incoming composite color video signal, a read clock and read start pulse generating circuit receiving reference video signals and being operative to generate read clock and read start pulses on the basis of such reference video signals, a memory into which the incoming color video signals are written for temporary storage in response to the write clock and write start pulses and from which the temporarily stored color video signals are read in response to the read clock and read start pulses, a circuit connected with the read clock and read start pulse generating circuit for provided added sync and sub-carrier signals which are inserted in the color video signals from the memory, and a phase control circuit for varying a phase of the separated horizontal sync signals with which the write clock and write start pulses are synchronized in accordance with changes in the relative phase of the read start pulses and the added sync signals.

Self-clocking serial decoder

Abstract: Apparatus for generating clocking pulses from serially transmitted data in which a level shift recurs with each bit. The circuit uses a coincidence of data word recognition and initial level shift to generate an initial clock pulse and thereafter uses the delayed clock pulses and level shift to produce subsequent clock pulses. A data word recognition circuit is also disclosed that employs a delay line for examining the profile of a synchronizing wave form.

Synchronizing circuit for a television receiver

Abstract: A synchronizing circuit arrangement for a television receiver having an oscillator which generates a clock signal the frequency of which is substantially higher than the line frequency and having a frequency dividing circuit which derives signals of the line frequency from the clock frequency by means of division. During a predetermined number of line periods a phase comparison stage determines the average value of the phase deviation between the received line synchronizing signal and a reference signal of the line frequency and applies the value obtained to a preset stage for adjusting in a subsequent time interval, for example one line period during the field blanking interval, the divisor by which the frequency dividing circuit divides the clock frequency. The clock frequency may be a multiple of the chrominance subcarrier frequency, in which case the oscillator is continuously readjusted by the phase comparison stage when the color killer circuit is operative, while the divisor is not changed.

Programmable multiple frequency ratio synchronous clock signal generator circuit and method

Abstract: A circuit and method for providing two or more synchronous clock signals whose respective frequency ratios can be readily changed with respect to a master clock signal frequency.

Video imaging apparatus having a pliant clock

Abstract: A video imaging apparatus for scanning an area during relative motion in a direction defining a track axis has at least two linear sensors each comprised of at least one array of charge coupled devices. The sensors are oriented substantially perpendicular to the track axis thereby defining a cross-track axis. The arrays are further fixed relative to each other and oriented for simultaneously scanning the same area. A master clock signal is used to readout the data produced by the first sensor. A phase-locked loop produces a slaved, pliant, clock signal for reading the data out of the second sensor. By varying the phase of the slaved clock signal relative to the master clock signal, mechanical offset between the two sensors is compensated. By varying the average frequency of the slaved clock signal relative to the master clock signal, scale differences between the two sensors are compensated. By cyclically varying the instantaneous clock frequency along the cross-track axis of the salved clock signal relative to the master clock signal, lens distortion is compensated. Thus, by utilizing the phase-locked loop to control plural characteristics of the slaved clock signal, the retreival of data from the sensors may be more accurately coordinated and the necessity of costly, complex, off-line post-processing avoided.

Centralized clock time error correction system

Abstract: The present disclosure describes a system for substantially eliminating clock signal timing errors occurring between the signal paths of the various cabinets or modules of a large, high speed digital synchronous data processor. Such errors result from the most part because of the long cable lengths needed for coupling the cabinets to a master clock source. The present system provides a measure of the signal delay from the output of the master clock source through the elements of a given cabinet and permits corrective measures to be made at a single location within the cabinet without the necessity of accessing the large number of elements contained therein.

Data acquisition circuit

Abstract: A data acquisition circuit is adapted to receive information data, a synchronization pulse and a clock pulse which is transmitted at twice as high as the transmission rate of the information data. The clock and synchronization pulses are processed into a conditioning pulse for a divide-by-two frequency divider so that it conditions the divider to respond to the clock pulse by generating a data acquisition pulse at a frequency corresponding to the transmission rate of the information data in a correct phase relationship therewith.

Multiple source clock encoded communications error detection circuit.

Abstract: Error detection circuit for detecting errors in a clock signal recovered from a self-cloking digital data signal. A first flip-flop (12) is alternately set and reset by the recovered clock signal (RF1) and by a transmitted clock signal (BFX) of supposedly equal frequency. The output of the first flip-flop (12) is sensed by a second flip-flop (14) at the end of a predetermined time period, as determined by the transmitted clock signal, for determining whether or not a transition in the recovered clock signal occurred within the predetermined time period. If no such transition occurred within the predetermined time period, the second flip-flop (14) outputs an error signal. The circuit in accordance with the present invention makes possible rapid detection of an error in the recovered clock signal (RF1).

Programmable clock rate generator

Abstract: A clock rate generator is described which can be programmed to provide an output clock that is N/M times the rate of a standard clock where N and M are integers. The generator comprises a counter (20), a programmable memory (30), reset logic (40) and a clocking control (50). A standard clock is applied to the counter (20) so that the counter (20) is advanced by one for each clock bit. The output of the counter is connected to the input lines of the programmable memory (30) where a pattern of binary ones and zeros are stored. The output of the programmable memory (30) is applied to the clocking control (50) to combine successive bits of the same polarity. The divisor M is determined by the number of standard clock counts between successive resets of the counter (20). The multiplier N is determined by the number of output cycles from the clocking control (50) between successive resets of the counter.

Electronic control apparatus with defined reset function

Abstract: To provide for starting of signal processing operations in a microprocessor (7), for example an automotive-type microprocessor, subject to frequent power interruptions, in which the processing operations are controlled by clock signals from a clock generator (1), and to insure that the microprocessor carries out its computation cycles only after the clock signal generator (1) provides clock signals at an adequate level appropriate for microprocessor operations, the level of the clock signals is sensed, for example in a peak rectifier (2, 3, 5) to reset the microprocessor when the clock signals have reached this level, thereby insuring commencing of processing cycles from a predetermined condition or state of the microprocessor at a time when adequate clock signals are available. The reset signal from the clock generator can be logically combined in a logic circuit (6) with externally generated reset signals, for example dependent on sufficient or suitable operating voltage being present for operation of the microprocessor from a power source (P), for example the battery of an automotive vehicle, to insure operation of the microprocessor only with adequate battery voltage being present, for example after termination of power drain by a starter motor.

Augmented phase-locked loop for very wide range acquisition and method therefor

Abstract: An augmented phase-locked loop for use with a data communication system in which the data is encoded into a plurality of symbol signals such that the channel on which transmission occurs is switched at a data clock rate between symbol signals and such that two like symbol signals cannot appear successively. The coincidental transitions between symbol signals are detected and are used to lock a phase-locked loop. If the integrated signal from a transition detector is greater than integration of the signal level of the pluses on each incoming channel at the frequency of the loop locking to a subharmonic is detected and causes a sweep circuit to drive an oscillator to sweep until the phase-locked loop locks on the correct data clock frequency. The frequency to which the loop is locked is used to clock a successive sampling of each input so that if the loop is locked on a harmonic of the correct data clock, the sequential repetition of a symbol signal on a channel is detected and is used to force an oscillator to sweep until the phase-locked loop is locked to the correct data clock frequency.

Device for increasing the operational security of a duplicated clock

Abstract: A device for increasing the operational security of a duplicated clock which comprises first and second clocks comprises in each clock a selector circuit with inputs connected to a filter and signal shaping circuit of each clock. Each selector circuit comprises two processing circuits and an output circuit which implements the following logic equation: w=(q1+q2)· w1+(q 1+ q2)·w2 in which: w is a clock signal from the selector circuit, w1 and w2 are the reconstituted clock signals produced by the first and second clocks, respectively. q1 and q1 are the direct and complemented output signals of the bistable of the first processing circuit, and q2 and q2 are the direct and complemented output signals of the bistable of the second processing circuit.

Memory access control apparatus

Abstract: In a microcomputer system with an asynchronous working central processing unit (CPU) and a cathode ray tube (CRT) display, a memory access control apparatus includes a memory, particularly a video RAM, a CRT controller connected to the CRT for accessing the memory, a system clock for generating system clock pulses which are supplied to the CPU, a multiplexing clock for generating multiplexing clock signals based on the system clock and having a frequency which is one-half the frequency of the system clock pulses, and a multiplexer connected to the CPU and the CRT controller through which the CPU and the CRT controller selectively access the memory in a time sharing manner according to the multiplexing clock signals.

Data reading apparatus for data transmission

Abstract: A data reading apparatus for data transmission, for reading digital data from a digital signal series obtained by comparing the level of an incoming transmission signal obtained through a transmission path with a reference level at a detector, comprises a reference clock pulse generator for generating a reference clock pulse having a period equal to substantially 1/M of a transmission digit period of the digital signal series, a detecting circuit supplied with the digital signal series and the reference clock pulse generated by the reference clock pulse generator, for generating a level variation detection pulse in phase synchronism with level varying points corresponding to rising edges and/or falling edges of the digital signal series, a frequency dividing circuit reset by the level variation detection pulse from the detecting circuit, for generating a data reading timing clock pulse with a period substantially equal to the digit period of the digital signal series and with a phase delayed with respect to the level variation detection pulse, by frequency-dividing the reference clock pulse from the reference clock pulse generator, and a data reading circuit for obtaining a data reading output signal by latching the digital signal series by the data reading timing clock pulse obtained from the frequency dividing circuit.

Synchronizing signal generator and an electronic musical instrument using the same

Abstract: A synchronizing signal generator includes a tape recorder which is adapted to record click signals in response to actuations of a manual switch. Counting clock signals go on while the click recorded signals are reproduced, especially during a length of time extending from receipt of a particular one of the click signals to receipt of the next succeeding click signal. The resultant count is divided by a given numeral value and then the quotient is stored. The clock signals developing between the respective click signals are further counted during the course of reproduction of the click signals from the tape recorder and a pulse signal is delivered whenever the instantaneous count coincides with the stored quotient. Tempo clock signals are obtained through the division of the pulse signal at a selected division ratio out of a plurality of division ratios. The tempo clock signals are fed to a sequencer which in turn generates a control voltage and gate signals synchronous with the tempo clock signals. A music synthesizer produces tone signals in synchronism with said tempo clock signals in response to the control voltage and the gate signals.

Self-clocked signature analyzer

Abstract: A method and circuit for using signature analysis testing techniques without deriving start/stop and clock signals from the device under test. In this invention, a start signal is derived from the output data stream by configuring that data stream to indicate when the test stream begins. The stop signal is derived by counting the predetermined number of data bit cells to be measured and issuing the stop signal when the count is reached. Data clock pulses are derived as a fraction of test system clock pulses at a frequency approximately equal to the bit cell frequency. The data clock pulse is located at the midpoint of the bit cell time so that the data stream is clocked into the signature analysis tester at a stable point.

Clocked tri-state driver circuit

Abstract: A tri-state driver circuit is provided having a first clock node; and a second clock node, the first and second clock nodes being adapted to receive first and second clock signals from respectively first and second clock signal sources, the first clock signal being periodic and having a first and second logic level, the second clock signal being the complement of the first clock signal. A float node is included and is adapted to receive a complement float signal (F) having a first and second logic level from a float signal source, an array of input nodes are also included, each input node being adapted to receive an input signal having a first and second logic level from a respective input signal source. An array of output nodes are included, each output node corresponding to a respective input node and being coupled to a respective load. The clocked tri-state driver circuit comprises: an enable node, a clocked power switch means coupled to the first and second clock signal nodes and the float node; the clocked power switch means being responsive to the first and second clock signal and the complement float signal first logic level for providing a clocked enable signal to the enable node; an array of driver circuit means for conditioning and transferring each respective input signal from a corresponding input node as an output signal to a corresponding output node when enabled, each respective driver circuit means being coupled to the enable node and enabled by the clocked enable signal, each respective driver circuit means being decoupled from the corresponding output node when not enabled, whereby the tri-state driver circuit operates to provide an array of output signals to an array of corresponding output nodes when enabled by the clocked enable signal first logic level at the enable node; the tri-state driver circuit also operating to decouple the output signals from the corresponding output nodes in response to the clocked enable signal second logic level thereby permitting the corresponding output nodes to be conditioned by voltage sources other than the tri-state driver circuit.

Clock selection control circuit

Abstract: A circuit which controls the selection and activation of one of a plurality of clock circuits arranged in copies. Selection circuitry is used to detect failure of an on-line clock circuit, scan a plurality of available clock circuits in a predetermined sequence and place the next available properly operating clock circuit on line. Control circuitry prevents erroneous clock selection during power-up/power down operations and enables predetermined clock circuit copies to be disabled.

High-speed low-power delayed clock generator

Abstract: A clock circuit for producing a high-level delayed clock output following an input clock employs an output transistor and pull-down transistor controlling an output node in response to the voltage on a drive node. The input clock is applied to this drive node by a decoupling arrangement, consisting of two series transistors. The first transistor isolates the input charge on a holding node, and the second of the series transistors transfers the charge to the drive node after the desired delay. The output node is held at zero until after the delay, with no unwanted voltage rise, and no d.c. power loss. A large capacitive load can be driven.

Flip-flop in current mode logic controlled by a transfer clock with auxiliary current applied to differential amplifier

Abstract: In order to avoid noise pulses which occur at the end of a clock pulse given a low signal level at the output of a clock-controlled flip-flop in ECL technology, an auxiliary current which is small in comparison to the primary current is supplied to a differential amplifier which is in a currentless condition during a clock pulse. As a result, the differential amplifier can be set to the respectively correct switch state before the end of the clock pulse.

Circuit for reproducing a clock signal

Abstract: A circuit for reproducing a clock signal from digital signals reproduced from a recording medium makes self-clocking possible. The circuit includes a phase lock loop having a voltage-controlled oscillator that generates an oscillation output at a frequency which is approximately equal to or an integral multiple of the frequency of the clock signal contained in the reproduced signal. A pulse generating device outputs pulses of a fixed amplitude, triggered by the leading or trailing edge of the input signal, to the phase lock loop. An oscillation device outputs pulses having approximately the same period as the clock signal period. The oscillation device is triggered by the leading or trailing edge of the input signal. A selecting device gates the output pulses of the oscillation device to the phase lock loop. The selecting device interpolates the output pulse spacing of the pulse generating device and the output pulses of the oscillation device so that a clock signal output is obtained from the phase lock loop.