Showing papers on "Clock domain crossing published in 1983"

Signal detection apparatus

Abstract: A phase detection function is obtained by performing two series retiming operations on a data input signal in accordance with a local clock and exclusive OR'ing the signals involved in the two retiming operations. The first exclusive OR'ing provides a variable pulse width signal and the second exclusive OR'ing provides a fixed pulse width signal which may be used as a reference. The combination of the two signals can then be used to provide an indication of phase of the clock with respect to the data. By taking the phase detected signal and supplying it in integrated format to a VCO and using the output of the VCO to provide the clock input to the retiming means, a circuit is provided which provides not only data regeneration, but also clock recovery from the data input and assures that the leading edge of the recovered clock is centered between positive going and negative going transitions of the data to be regenerated. This regeneration can take place in the form of jitter reduction, pulse amplitude restore and pulse width restore. The same circuitry can also, through the addition of one feedback loop, provide data equalization.

Synchronization of real-time clocks in a packet switching system.

Abstract: A packet switching system in which a remote real-time clock is accurately synchronized to a standard real-time clock via X.25 (CCITT) controlled high-speed transmission links. Synchronization is achieved by the transmission of an interrupt packet and a data packet between a remote processor controlling the remote real-time clock and an administrative processor controlling the standard real-time clock. Synchronization involves the following steps: (1) assembling an interrupt packet comprising the least significant bits of the remote real-time clock for transmission to the administrative processor by the remote processor, (2) calculating bits representing the difference between the transmitted least significant bits of the remote real-time clock and the least significant bits of the standard real-time clock by the administrative processor, (3) assembling a data packet comprising bits representing the state of the standard real-time clock and the difference bits for transmission to the remote processor by the administrative processor, (4) adding the difference bits to the bits representing the state of the remote real-time clock by the remote processor, and (5) adding a predefined value to the most significant bits of the remote real-time clock by the remote processor if the transmitted least significant bits of the standard real-time clock are numerically greater than the least significant bits of the remote real-time clock.

Variable frequency microprocessor clock generator

Abstract: A microprocessor based system (10) includes a central processing unit (CPU) (12) that controls the operation of a display (20) through a controller (22). System storage is provided with a read only memory (16) and random access memory (14). A reference clock signal is generated by a clock generator (26) which is input to a clock control circuit (24). The control circuit (24) generates a CLK signal that is connected to the clock input of the CPU (12). The control circuit (24) is operable to reduce the rate of the clock input to the CPU (12) when accessing the controller (22) which has a slower speed of operation than the random access memory (14). The control circuit (24) includes a programmable counter (38) for generating a gating signal after counting a predetermined number of cycles of the reference clock signal and initiating a count cycle only after generation of the gating signal. Generation of the gating signal by the counter (38) causes a latch circuit (68) to become transparent during selected transitions of the CLK signal. The control circuit (24) also provides for overriding the programmable counter (38) via an event counter circuit (56) which is effective to generate the gating signal independently of the programmable counter (38) after counting a predetermined number of count cycles of the programmable counter (38). The control circuit (24) is thereby effective to reduce the rate of the CLK signal as input to the CPU (12) and to retain the reduced rate of the CLK signal for a time period sufficient for the CPU (12) to access peripheral devices of low operating speed. Thus, the CPU (12) is able to control peripheral devices that have different maximum rates of operation.

Performances of the Delay-Line Multiplier Circuit for Clock and Carrier Synchronization in Digital Satellite Communications

Abstract: This paper is concerned with clock and carrier synchronization in digital satellite transmissions, using the delay-line multiplier circuit. For clock recovery from baseband signal, with random data, a closed form formula is derived which gives the spectrum after multiplication, for any arbitrary pulse shape. This spectrum contains spectral lines at the clock frequency and its harmonics, and a continuous part which is the pattern noise. This pattern noise may be decomposed in noise in phase with the recovered clock, and noise in quadrature whose power spectral density is always zero at zero frequency. The effect of Gaussian noise on the channel is taken into account to calculate signal-to-noise ratio at the clock frequency as a function of the classical parameter E/N_{o} . With a modulated input carrier, the signal at the output of the delay-line multiplier may be separated into two parts: a low frequency signal that contains clock information and a bandpass spectrum signal around twice the carrier frequency that contains carrier information, when possible. Spectrum and signal-to-noise ratio in carrier recovery are studied for BPSK and offset quadrature modulation.

Data communication system and method and communication controller and method therefor, having a data/clock synchronizer and method

Abstract: A communication system and method is provided, in which synchronous (i.e., clocked) serial digital data may be sent and received from any given node to any other given node along a multinode loop of any desired mode quantity, with each node being capable of and maintained ready to assume the role and function of master node to provide the time-base or master clock for the loop. One node will serve as master node and all other nodes as slave nodes until the master becomes inoperable in its master clock function or until it is removed from the loop, at which time another node will assume the role of master node, and this status will continue as above-indicated. Small loop size is accommodated by adding a suitable delay to retransmitted data at the master node. Each node has clock recovery and both recovered clock/data synchronization means and its on-board master clock/data synchronization means (which latter is close to the same frequency at each node, but independent in frequency and phase at each node) to enable each node to serve as either master or slave node by internal switching selection of communication control output of either recovered clock data or master clock data for use and retransmission at each node, dependent on its instant self-intended role as slave or master. Master clock data synchronization at the master node is effected by shifting recovered clock data by a selected phase as a function of phase difference between the instant master node master clock and recovered clock at such master node, the selected phase shift being an amount sufficient to enable effective sampling by the master clock, to thereby provide absolute phase synchronization of receive data with master clock for internal serial processing, utilization, and retransmission by the instant master node. Each instant slave node has its own on-board such master clock data synchronizing means which may be maintained on standby, for enabling each assumption of the master node role, as may be required.

Digital PLL decoder

Abstract: A digital PLL technique to provide an effective sampling interval and resolution shorter than the driver clock period. A multi-phase driver clock provides a clock signals phase-offset from each other. One clock output signal is used as the driver clock to clock an input sampler. A pattern of bit samples before, nominally at, and after a predicted clock edge indicates whether a leading or lagging phase should be substituted for the present driver clock signal. The phase difference is substantially less than the period of the fastest clock presently available to generate satisfactory shaped pulses.

Synchronizing large VLSI processor arrays

Abstract: Highly parallel VLSI computing structures consist of many processing elements operating simultaneously. In order for such processing elements to communicate among themselves, some provision must be made for synchronization of data transfer. The simplest means of synchronization is the use of a global clock. Unfortunately, large clocked systems can be difficult to implement because of the inevitable problem of clock skews and delays, which can be especially acute in VLSI systems as feature sizes shrink. For the near term, good engineering and technology improvements can be expected to maintain the feasibility of clocking in such systems; however, clock distribution problems crop up in any technology as systems grow. An alternative means of enforcing necessary synchronization is the use of self-timed, asynchronous schemes, at the cost of increased design complexity and hardware cost. Realizing that different circumstances call for different synchronization methods, this paper provides a spectrum of synchronization models; based on the assumptions made for each model, theoretical lower bounds on clock skew are derived, and appropriate or best-possible synchronization schemes for large processor arrays are proposed. One set of models is based on assumptions that allow the use of a pipelined clocking scheme, where more than one clock event is propagated at a time. In this case, it is shown that even assuming that physical variations along clock lines can produce skews between wires of the same length, any one-dimensional processor array can be correctly synchronized by a global pipelined clock while enjoying desirable properties such as modularity, expandability and robustness. This result cannot be extended to two-dimensional arrays, however—the paper shows that under this assumption, it is impossible to run a clock such that the maximum clock skew between two communicating cells will be bounded by a constant as systems grow. For such cases or where pipelined clocking is unworkable, a synchronization scheme incorporating both clocked and “asynchronous” elements is proposed.

Clock pulse signal generator system

Abstract: A clock pulse generator system for providing a highly stable clock signal consists of two separate redundant clock signal generators which are controlled to operate in dead synchronization with each other. A microprocessor controlled digital phase lock loop operates to control each of the two clock signal generators and selects among a plurality of operating states such that the average dynamic phase difference in the two clock pulse signals generated is practically zero. Furthermore, the instantaneous dynamic phase difference does not exceed the phase noise of the voltage controlled crystal oscillators of the phase lock loops and, in one embodiment, is normally less than ten pico seconds, each phase lock loop comprising means for performing a fine, as well as coarse, phase comparison among internally or externally generated reference signals, only one of which is the highly stable clock signal output.

Clock source with automatic duty cycle correction

Abstract: A clock source for timing and synchronizing the operation of digital data processing equipment and having automatic duty cycle correction is described A source of signals provides clock signals at a predetermined frequency A buffer circuit provides the true and complement clock signals to low pass filters that function to filter the true and complement clock signals to DC levels proportional to the duty cycle of the source signals The DC voltages represent instantaneous deviation voltages from a known reference and are applied to a differential amplifier circuit for providing a feedback signal for adjusting the duty cycle of the clock output pulses that are available One embodiment has the source of signals directly coupled to the buffer circuitry and utilizes the feedback signal to adjust the duty cycle of the signal source circuitry A second embodiment has the source signals capacitively coupled to the self-correcting circuitry and the feedback signals adjust the duty cycle of the clock output signal

Multiple redundant clock system comprising a number of mutually synchronizing clocks, and clock circuit for use in such a clock system

Abstract: A multiple redundant clock system comprises at least n=4 clocks and is self-synchronizing and fault tolerant against the failure of at the most 1/2(n-1) clocks. Each clock comprises an oscillator circuit which activates a dividing circuit at the end of each period in order to form its own clock signal on the output of the dividing circuit. Each clock furthermore comprises a deviation-determining device which compares the own clock signal with the clock signals originating from the other clocks in the system. When an excessively large number of the other clock signals deviate during the first half of the (own) period, the own oscillator circuit is decelerated. When an excessively large number of the other clock signals deviate during the second half of the own period, the own oscillator circuit is accelerated.

MOS Analog switch driven by complementary, minimally skewed clock signals

Abstract: An MOS analog switch utilizing two transmission gates which are compensated by a third transmission gate is provided. The transmission gates may be either single or complementary conductivity type transmission gates and are controlled by complementary clock signals. A method and apparatus for minimizing clock skew thereby reducing error voltages caused by parasitic capacitance are provided.

Signal quality monitoring device

Abstract: The error rate of a signal is monitored by sampling an input signal with a first clock and also with second and third clocks phase delayed in equal but opposite directions with respect to the first clock, and then logically combining the first through third sampled outputs in order to obtain an error signal.

Clock recovery arrangement

Abstract: A clock recovery arrangement particularly suitable for recovering a clock signal from Manchester-encoded data. The system includes a locally generated clock at twice the data rate. This locally generated clock is phase locked to the incoming data transitions. Then, the locked locally generated clock is divided by two to produce a clock signal corresponding to the data rate. A clock flipper circuit operating according to a predetermined algorithm determines whether to change the polarity of the clock signal to provide a correct polarity recovered clock.

Control of data access to memory for improved video system

Abstract: In a video computer system having a RAM chip with a shift register connected to its serial output terminal and actuated by a first clock circuit, a second different clock circuit is included to cause the data bit in the first stage of the register to also appear at the serial output terminal of the chip. Accordingly, signals from the first clock circuit will then sequentially transfer data bits from the shift register, to the output terminal of the RAM chip, without omitting or losing a clock cycle, or a portion thereof.

Clock recovery system for TDMA satellite communication system

Abstract: A clock signal in a TDMA burst signal is recovered by using the frequency and phase information extracted by taking a moving average of plural bursts received previously from the same earth station. The system has memory storage for storing frequency and/or phase information of a moving average of plural bursts received previously, and clock signal necessary to demodulate the present burst is recovered by using output of the memory storage. Thus, the synchronized clock signal for demodulating the received burst is obtained in a short time, or even a clock recovery bits in a burst may be removed. The establishment of the synchronized clock signal is indicated by a synchronization circuit which provides the establishment signal for each burst after receiving a predetermined plurality of bursts from the same earth station.

Clock generating circuit providing a boosted clock signal

Abstract: A clock generating circuit includes a switch control circuit controlling a C-MOS circuit including first and second transistors having first and second conductivity types, respectively. Also included in the clock generating circuit is a bootstrap capacitor having a first end connected to the junction between the first and second transistors. The switch circuit includes a third transistor, having the first conductivity type, connected between the gate of the first transistor and the junction between the first and second transistors, and a fourth transistor, having the second conductivity type, connected between the gates of the first and second transistors. The gate of the second transistor is connected to receive an input clock signal and the gates of the third and fourth transistors are connected together to receive a delayed clock signal produced by delaying the input clock signal. The second end of the bootstrap capacitor is connected to receive a further delayed and inverted clock signal. When the delayed clock signal has a first value, the switching circuit connects the gates of the first and second transistors together and an output signal with a first level is produced at the junction of the first and second transistors. When the delayed clock signal reaches a second level, the switching circuit connnects the gate of the first transistor to the junction of the first and second transistors and the bootstrap capacitor boosts the output signal to a second level.

Fault testing a clock distribution network

Abstract: A method and apparatus for fault testing a clock distribution network which provides a plurality of clock signal lines to the logic networks which comprise a data processor. The fault testing apparatus includes a decoder for selecting one of the clock signal lines to be tested, and a test latch which is clocked by the selected clock signal line. The selected clock signal line is tested by setting the test latch to a first logic value (e.g., binary ZERO) and maintaining a second logic value (e.g., binary ONE) at the test latch input. If the second logic value is stored in the test latch when the clock distribution network is inhibited, then a stuck-on fault is indicated for the selected clock signal line. If the second logic value fails to be stored in the test latch when the clock distribution network is enabled, then a stuck-off fault is indicated for the selected clock signal line. Each clock signal line in the clock distribution network may be tested in this manner.

Clock signal reproducing circuit for a player reproducing information of a disc

Abstract: A clock signal reproducing circuit for a player reproducing information of a disc reproduces a clock signal from a signal reproduced from a disc via a pickup head. The clock signal reproducing circuit comprises clock signal generating circuit for generating a clock signal having a period of about 1/n (n being an integer) of the signal reproduced from the disc, a first detecting circuit which, in response to the signal reproduced from the disc via the pickup head and the clock signal delivered from the clock signal generating circuit, detects a phase error between the two signals containing a component for 1/2 period of the clock signal, a second detecting circuit which, in response to the clock signal delivered from the clock signal generating circuit, detects the component for 1/2 period of the clock signal at a timing when the first detecting circuit detects the phase error, and a combinating circuit which cancels the component for 1/2 period of the clock signal by combining output signals of the first and second detecting circuits thereby to provide only the phase error component. A phase locked loop is operated in response to this phase error component such that the clock signal and the input signal reproduced from the disc are in phase with each other.

4-Phase clock generator

Abstract: A 4-phase clock generator comprises four gates for generating four clock signals from a master clock signal. The logic levels of four clock signals change in predetermined order after the master clock signal changes from a first logic level to a second logic level and they change in inverse order after the master clock signal changes back to the first logic level. The four clock signals are suitable to operate a shift register without making the adjoining transfer gates of the shift register conductive simultaneously.

Master/slave clock system

Abstract: A master/slave clock system including a slave clock configured for inexpensive and reliable control from the master. Each slave clock has an unregulated d-c supply adapted to be supplied with a-c power from the master clock. Threshold switching means in each slave clock is coupled across the d-c supply to sense an abnormally low d-c voltage level intentionally created by lowering the a-c supply level from the master. The threshold switching means switches the clock from the normal operating mode to the set mode where time is incremented at a predetermined rate for a duration controlled by the master clock in order to controllably set all slave clocks in the system to the correct time of day. The system conveniently allows all slaves to be reset to the same time when time is reset at the master, provides for automatic recovery after power failures, and provides a convenient means for automatically resynchronizing all slave clocks twice a day.

Synchronous clock generator for digital signal multiplex devices

Abstract: An exemplary embodiment includes a first binary counter whose counting period corresponds to a block length of a pulse frame, a block counter controlled by the first counter, and a logic element for generating working clock signals, wherein the counters are switchable for employment in different multiplex systems and the logic element gates out the working clock signals for different multiplex systems.

Prioritized clock selection circuit

Abstract: A clock selection circuit which selects and enables one of a plurality of clock circuits in response to initialization by a processing unit or detection of failure of an on-line clock circuit. The clock circuits are selected on the basis of a priority arrangement. The clock circuit failure is detected by a retriggerable monostable multivibrator and the selection priority is based on time delays generated by programmed counters associated with each clock circuit.

System for detecting and recovering a transmitted signal

Abstract: What is disclosed is a system for recovering encoded data from a transmitted signal A clock regenerating circuit regenerates a clock signal from the data bits encoded in the signal The regenerated clock signal is used to synchronize an up/down with each individual data bit When a data bit is at a logic "H", the counter counts from a predetermined value in an upward direction and when the data bit is at a logic "L", the counter counts in a downward direction from a predetermined value The count after each bit-time is used to provide a signal representative of the logic state of that data bit Accordingly, a reproduced data signal can be accurately obtained

Non-pll concurrent carrier and clock synchronization

Abstract: Concurrent carrier and clock synchronization are derived from an input signal in interdependent loops without the use of phase look loop (PLL) circuitry in order to improve operation at higher bit rates. An acquisition detection signal is generated only in response to predetermined minimum errors in both the received signal amplitude and the recovered carrier phase.

Master clock generator for telecommunications system

Abstract: A very stable master clock for satellites is disclosed. Time division multiple access techniques are used to permit individual earth stations to be received by the satellite in separate non-overlapping time slots. The satellite switched time division multiple access systems are compatible with the onboard satellite clock by providing a comparator control logic loop to produce a signal representing the phase difference between the onboard oscillator clock and the earth station. Control signals are generated to correct the voltage controlled oscillator onboard the satellite.

Clock recovery apparatus

Abstract: A clock recovery apparatus for generating an output clock signal locked to the phase and frequency of an input data rate which comprises a sequence of encoded data signals, comprises a data detector (10) for detecting the data signals, an oscillator (14), for generating a first clock signal having a frequency of oscillation representative of the value of an analog signal, and a phase detector (16) comprising a memory (56) and a register (58). The register is responsive to the first clock signal to generate the output clock signal and the memory is responsive to the count of the register and the data detector to determine the relative phase relationship between each data signal and the output clock signal and to store information pertaining to the relative phase relationship. A counter (30) contains a count and a converter (34) is responsive to the count to generate the analog signal. The memory is responsive to the relative phase relationship of a data signal and to the stored information pertaining to a previous relative phase relationship to operate the counter to increment or decrement selectively the count therein to alter the frequency of the first clock signal.

Electronic controller for use with a surgical laser system

Abstract: The present invention is an electronic controller for use with a laser system which includes a mechanical triggering device and which generates a beam of light energy in the infrared spectrum The electronic controller includes a laser modulator which turns the laser system on and off at a frequency rate of two hundred cycles per second and a trigger/reset circuit which is electrically coupled to the mechanical triggering circuit The trigger/reset circuit provides a trigger signal in its triggered state and a reset signal in its untriggered state The electronic controller also includes a clock circuit which is electrically coupled to the triggering circuit and which provides clock signals in response to the trigger signal and a one-shot monostable, multivibrator circuit having an RC timing circuit which is electrically coupled to the clock circuit and which controls the pulse width of its output signal in a range of 0005 seconds and 01 seconds in response to the clock signals The electronic controller further includes a counter which is electrically coupled to the one-shot monostable, multivibrator circuit and which counts each of the clock signals and a comparator which is electrically coupled to the counter in order to compare the number of the counted clock signals to a selected number and to the clock circuit and which is electrically coupled to the clock circuit, so that, when the number of the counted clock signal equals said selected number, the comparator provides a clock inhibit signal in order to inhibit the clock circuit from providing any more clock signals

Read clock producing system

Abstract: In a read clock producing system for generating a read clock signal which is used for extracting a digital information portion of a digital coded signal, the system comprises means for delaying a pulse obtained by comparing data with a certain threshold level, means for generating a clock pulse having a pulse width proportional to the delay, said generating means including a frequency division circuit, flip-flop and EOR means for comparing the pulse width with a predetermined pulse width, a differential amplifier for comparing the data with a second threshold level adapted to change in accordance with the above comparison, and the control means for controlling the delay by the use of an output from said comparison.

Clock monitor circuit and method

Abstract: A clock monitor circuit and method for providing an indication at the output thereof of the presence of an input clocking signal. If the clock input is operating properly, two charge storage nodes will be charged and the output of the circuit will be high. If the clock input is stuck, the output of the clock monitor circuit will be low.

Clock signal synchronization apparatus and method for decoding self-clocking encoded data

Abstract: A clock signal synchronization apparatus for decoding self-clocking encoded data generates data signals identical in frequency with the encoded data but progressively offset in time with respect to the encoded data signal. The delayed data signals are responsive to the clock rate of a clock signal generating means so as to be advanced or delayed in time with respect to the encoded data when the clock signal generating means is not synchronized with the encoded self-clocking data. The instantaneous binary states of the encoded data and the delayed data signals are sampled in parallel to detect one of a predetermined number of distinct trigger codes. The signals are continuously sampled to detect a correct following code after the detected trigger code to indicate that the clock signal is synchronized with the encoded, self-clocking data. Error codes will be detected prior to the correct following code for each distinct trigger code when the clock signal is delayed or advanced with respect to the encoded data. The amount of time that an error code is present is used to vary the clock rate of the clock signal generating means to bring it into synchronization with the encoded self-clocking data.