Showing papers on "Comparator applications published in 2001"

Adaptive loop response in switch-mode power supply controllers

Abstract: The output terminal of an error amplifier ( 32 ) is coupled to the inverting input of a comparator circuit ( 34 ). Additionally, a clamp circuit is coupled between the output terminal of the error amplifier ( 32 ) and circuitry connected to the non-inverting input of the comparator circuit ( 34 ), to clamp the voltage there between to a predetermined voltage level. This circuit arrangement provides improved controller closed loop response that is adaptive to the power supply ( 10 ) output voltage.

Data strobe receiver

Abstract: A data strobe receiver that includes a first comparator. The first comparator has a first input that is coupled to a first reference voltage. The first comparator has a second input that is coupled to a data strobe. The first comparator also has an output. The data strobe receiver also includes a delay element. The delay element has an input that is coupled to the output of the first comparator. The delay element also has an enable input and an output. The data strobe receiver also includes a second comparator. The second comparator has a first input that is coupled to a second voltage reference. The second comparator has a second input that is coupled to the data strobe. The second comparator also has an output. The data strobe receiver also includes a flip-flop. The flip-flop has a preset input that is coupled to the output of the second comparator. The flip-flop has a clock input that is coupled to the output of the delay element. The flip-flop also has an output that is coupled to the enable input of the delay element.

Circuit Design of a High Speed and Low Power CMOS Continuous-time Current Comparator

Abstract: Current comparator is a fundamental component of current-mode analog integrated circuits. A novel high-performance continuous-time CMOS current comparator is proposed in this paper, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. A MOS resistor is used as the CMOS complementary amplifier's negative feedback. Because the voltage swings of the CMOS complementary amplifier are reduced by low input and output resistances, the delay time of the current comparator is shortened. Its power consumption can be reduced rapidly with the increase of input current. Simulation results based on 1.2 mm CMOS process model show the speed of the novel current comparator is comparable with those of the existing fastest CMOS current comparators, and its power consumption is the lowest, so it has the smallest power-delay product. Furthermore, the new current comparator occupies small area and is process-robust, so it is very suitable to high-speed and low-power applications.

Constant-frequency control circuit for a switching voltage regulator of the hysteretic type

Abstract: The invention relates to a control circuit for a hysteretic switching voltage regulator, which comprises a logic circuit driving an output stage; a hysteresis comparator comparing the voltage value at the output of the regulator with a reference voltage; a current sensor for sensing, through a comparator, the current drain of a load connected to the output of the regulator. This control circuit further comprises a device for adjusting the hysteresis range of the hysteresis comparator, and a hysteresis frequency sensing and controlling logic portion connected to the output of the hysteresis comparator, the logic portion acting on the frequency adjusting device.

Equalization of a transmission line signal using a variable offset comparator

Abstract: According to an embodiment, an equalization loop has a comparator with an input to receive a transmission line analog signal level. The comparator has a substantially variable offset that is controllable to represent a variable reference level. An output of the comparator provides a value that represents a comparison between the transmission line analog signal level and the variable reference level.

Low-power substrate bias generator disabled by comparators for supply over-voltage protection and bias target voltage

Abstract: A substrate bias generator has a ring oscillator disabled when a supply over-voltage condition is detected by a supply comparator, or when a target substrate voltage is reached. A substrate comparator compares the substrate voltage to a reference generated by a p-channel sense transistor that is independent of the substrate voltage. The substrate is sensed by an n-channel sense transistor with only its bulk connected to the substrate voltage. Current sources for the sense transistors and comparator are controlled by bias voltages generated by a voltage divider that switches from a high-power state to a low-power state once the substrate target is reached. Feedback turns off a high-current resistor, limiting current to that passing through a low-current resistor. The bias voltages are adjusted to reduce current to the sense transistors and comparator, reducing power. High current and power are used for fast sensing before the substrate target is reached.

Comparator with offset voltage

Abstract: A comparator according to the present invention can generate an output signal of low or high level by comparing a first and second input voltages that have a common voltage. An input stage circuit of a comparator according to the present invention receives a common voltage detection signal. The common voltage is supplied with a first offset voltage when the common voltage detection signal is on low level, and the common voltage is supplied with a second offset voltage when the common voltage detection signal is on high level. Then, the input stage circuit performs amplification to output a voltage difference between the first input voltage and the second input voltage to the comparator. Accordingly, the comparator with offset voltage according to the present invention can sufficiently amplify the input signal difference of low common voltage by selectively applying different offset voltages to a common voltage in accordance with the common voltage level of the input signal. The present invention can be applied to a comparator with offset voltage and an analogue comparator having a differential input stage.

Voltage regulator for low-consumption circuits

Abstract: A voltage regulator having a comparator with an output terminal that is the output of the regulator, terminals for connection to a voltage supply, a source of a reference voltage connected to an input terminal of the comparator, and a feedback circuit connected between the output terminal and the other input terminal of the comparator. To prevent transients upon the transition from the standby state to the active state, there is provided a second reference-voltage source that provides a reference voltage substantially equal to that of the first source, a switch for connecting the second source to the other input terminal of the comparator, and a control circuit that can activate the supply of the regulator and can close the switch for a predetermined period of time when the supply of the regulator is activated.

Reverse load current isolation circuit for parallelable power supply

Abstract: An isolation device feasible for protecting a parallelable power supply from a reverse current comprises a field-effect transistor (FET) coupled in series between a voltage output terminal of the parallelable power supply and a load, and a transistor control circuit including a voltage comparator for detecting if a reverse current is flowing through the FET, a duty comparator circuit for detecting if an infinitesimal reverse current which is undetectable by the voltage comparator circuit is flowing through the FET, a transistor driving circuit for performing a logic AND operation with an output state of the voltage comparator circuit and an output state of the duty comparator circuit to drive the FET to turn on or off in response to the result of the logic AND operation, and an auxiliary circuit for driving the FET to turn off when the parallelable power supply is short-circuited.

Continuous time delta-sigma modulator

Abstract: An analog-to-digital converter (170) that employs delta-sigma technology, and has particular use in a receiver for a wireless telecommunications system. The converter (170) includes a delta-sigma modulator (172), having a summing junction (180) that receives the analog input signal to be converted. A feedback from the output of a comparator (186) is subtracted from the analog input signal to generate a difference signal that is then filtered, amplified and applied to the comparator (186) for digital conversion. A sample and hold circuit (184) receives the difference signal and holds the signal for a predetermined period of time so that the input to the comparator (186) is stable. A differential limiting amplifier (188) is employed to make the high data rate output of the comparator (186) stable. The differential limiting amplifier (188) can be within the comparator (186) itself, or in the feedback path. In one embodiment, the differential amplifier (188) employs a Schottky diode clamp (226).

Pulse width modulated voltage regulation circuit and related methods

Abstract: A circuit and method for providing a regulated output voltage is described. The circuit includes a capacitor array, a comparator and an output control module. The capacitor array receives an input voltage, first and second control signals, and generates a regulated output voltage in response. The comparator compares the regulated output voltage and a reference voltage, and generates a comparator signal in response. The output control module receives the comparator signal and the first control signal. In response, the output control module provides the second control signal to the capacitor array.

A method for controlling a vehicular generator, an external controller and a vehicular power generation controlling device

Abstract: When a transistor is turned ON, a predetermined voltage VCL is applied to a minus terminal of a voltage comparator through a C terminal. A predetermined voltage Vd (Vd>VCL) is applied to a plus terminal of the voltage comparator, and an output of the voltage comparator changes from a low level to a high level. Such change is detected by a trigger detection circuit so as to activate a timer circuit, and an output of the timer circuit transitions to the high level during a predetermined time. Thereby, a transistor is changed to an on-state, a reference voltage Vb of an adjustment voltage applied to a plus terminal of a voltage comparator is set generally to 0V, and a transistor is turned OFF, so as to temporarily suspend a power generation state of a vehicular generator.

Multi-level receiver circuit with digital output using a variable offset comparator

Abstract: A number of comparators are provided where each has a differential input coupled to receive a transmission line analog signal level. Each comparator has substantially variable offset that is controllable to represent a respective variable reference level, without requiring a separate input to receive a voltage reference level. An output of each comparator is to provide a value that represents a comparison between the transmission line analog signal level and the respective reference level.

Very low-power comparison device

Abstract: A device for comparing two input signals includes a first comparator with differential outputs to whose inputs the signals are applied. The first comparator is followed by a second comparator delivering an output logic signal of the device. Each comparator includes at least one input differential stage, and each stage has two arms biased by a bias current generator. The comparison device may also include at least one additional current supply circuit associated with an arm of the input differential stage of the first comparator to copy the current of the arm and add it, with a multiplier factor, to the bias current of the input differential stage of the second comparator. This facilitates a corresponding switch-over.

Voltage margin testing of a transmission line analog signal using a variable offset comparator in a data receiver circuit

Abstract: A data receiver circuit having a comparator that exhibits substantially variable offset that is controllable to represent a variable reference level, without a separate input to receive a reference voltage level. The comparator output provides an indication of the comparison between a fixed voltage level applied to its differential signal input and the variable reference level. While changing an offset code that is fed to an offset control input of the comparator, and while applying a fixed voltage level that represents a symbol in the transmission line analog signal, a value of the offset code which causes the output of the comparator to change states is captured. A similar process may be repeated for different symbol values that can be transmitted, such that an indication of the voltage margin may be obtained as a difference between two captured offset codes. Circuitry to perform the process may be provided on-chip to the receiver circuit.

Pre-amplifier design for high-speed analog-to-digital converters

Abstract: The present invention overcomes the gate leakage drawback existing in advanced CMOS technologies to achieve extremely high-speed analog-to-digital conversion. The circuit and method employ an input offset storage (IOS) technique to calibrate the differential comparator device during an auto-zero cycle. The reference voltage and offset voltages are stored on capacitors coupled to the inputs of the differential comparator device during the auto-zero cycle. A source follower is placed between each capacitor and the inputs to the differential comparator device. The source followers are selected to prevent leakage from the capacitors during a conversion mode. Additionally, switches utilized in feedback loops for auto-zeroing the differential comparator are also selected to prevent leakage of the capacitors in the conversion mode.

Switched power supply with voltage regulator having pwm with hysteretic loop controller and method for operating and using same

Abstract: A switched power supply (40) has a pulse width modulator to adjust a pulse width that controls the output voltage (104). The width modulator includes a comparator (66) that compares a signal (104) indicating a value of the power supply to a ramp wave (69). An output of the comparator (66) is a signal containing a time width proportional to the output of the power supply. Additionally, a first comparator (90) compares the output voltage (42) to a first reference voltage (94). When the output voltage (42) exceeds the first reference voltage (94), the first comparator (90) changes state. A second comparator (88) compares the output voltage (42) to a second reference voltage (92). When the second reference voltage (92) exceeds the output voltage (42), the second comparator (88) changes state. The pulses are width modulated to first or second width limits in response to changes of output states of the first and second comparators.

On-chip histogram testing

Abstract: Circuitry for generating a histogram of output codes produced by an analog/digital converter (ADC) on an integrated circuit chip includes a comparator, disposed on the chip together with the ADC. A first input of the comparator is coupled to receive output codes from the ADC, while a second input is coupled to receive a sequence of target codes covering at least a portion of a range of the output codes. A pulse generator is disposed on the chip together with the ADC and the comparator, and coupled to receive the output of the comparator and, when the output is in the first state, to generate pulses for output from the chip at a pulse rate determined by a clock signal of the ADC.

Carrier modulator for use in a transmitter or transceiver

Abstract: A transmitter has a quadrature modulator that provides a modulated signal at a first frequency. The transmitter has a phase locked loop, of which a voltage controlled oscillator is coupled after the phase comparator of the phase locked loop, and further has a power amplifier in the transmit signal path of the transmitter. The phase locked loop further has a down-converter in the feedback path, from the output of the power amplifier, and a feedback input to the phase comparator. The transmitter further has an amplitude restoration arrangement, that restores amplitude information contained in the feedback signal provided by the down-converter. In operation, the phase locked loop replicates, at the carrier frequency, angle information contained in the quadrature modulated signal, and the amplitude restoration arrangement controls the gain of the transmit power amplifier such that input signals at the phase comparator substantially are equal.

Redundant comparator design for improved offset voltage and single event effects hardness

Abstract: An analog comparator architecture has improved immunity to single event effects and variations in input offset voltage. A conventional single analog comparator-based circuit is replaced with plural comparators, driving a “majority vote” logic block. The effective input offset voltage of the multi-comparator design is the middle one of the individual comparators' input offset voltages. A single event upset on any comparator may momentarily perturb its output into the incorrect state; however, the output of the majority voting logic block will remain in the correct state, as only one comparator is upset. In addition, where a heavy ion strike on any comparator's bias current source causes a momentary loss of bias current, this upsets only one comparator, so that the output of the voting logic block is unaffected.

Differential input data slicer

Abstract: Automatic slice level control response to differential input signals is provided to remove in-phase noise and effects on S/N ratio Analog differential input signals Vinp and Vinn are inverted with respect to each other and applied to input terminals in 1 and in 2 of a comparator via resistors R 1 and R 2 . A data stream is provided giving DSV=0. A charge pump is driven by a digital signal from the comparator. A transconductance amplifier produces output current Itrc 1 and Itrc 2 that are mutually differential signals and in proportion to the voltage difference between the output voltage Vcp from the charge pump and a reference voltage Vref. The output currents are supplied to the input terminals in 1 and in 2 of the comparator to provide a DSV=0. The analog differential input signals are binarized by the comparator to remove in-phase noise

Semiconductor device with test mode for performing efficient calibration of measuring apparatus

Abstract: A clock buffer includes: a comparator circuit comparing complementary clock signals CLK and /CLK with each other to output an internal clock signal used in a normal operation; a comparator circuit comparing a reference potential Vref and clock signal CLK with each other; and a comparator circuit comparing reference potential Vref and clock signal /CLK with each other. A phase comparator circuit compares the complementary clock signals with each other in respect to phase. An input/output buffer outputs an output of the phase comparator circuit to a data output terminal in a test mode. Therefore, there can be realized a test mode for performing efficient calibration of a measuring apparatus.

Flexible converter routing apparatus, system and method

Abstract: The present invention is directed to a flexible converter suitable for providing a routing function. A flexible converter of the present invention may provide a desired output utilizing a variety of methods, systems and apparatus without departing from the spirit and scope of the present invention. A routing apparatus may include a converter, at least one comparator and a controller. The converter is capable of providing an output supply from an input supply coupled to the converter, the output supply capable of routing between a first output and a second output. At least one comparator is coupled to the output supply of the converter, the comparator capable of measuring at least one power characteristic of the first output and the second output to a first electrical device and to a second electrical device. The controller is coupled to the comparator; the controller being capable of implementing a process within the converter such that the first output is routed to the first electrical device and the second output is routed to the second electrical device. The first output and the second output are monitored with the at least one comparator and the first output to the first electrical device and the second output to the second electrical device are re-routed based upon the monitoring by the comparator.

Comparator circuits having non-complementary input structures

Abstract: A non-complementary comparator includes an evaluation element such as a memory cell, a differential amplifier, or another type of circuit capable adapted to perform an evaluation function, and at least first and second input legs each coupled to a corresponding one of a first and second node of the evaluation element. The first and second input legs have non-complementary structures relative to one another, with each of the non-complementary structures having associated therewith a variable parameter, e.g., a variable resistance, variable current or variable voltage, having a value that is a function of a corresponding input signal. The evaluation element performs a comparison of at least first and second inputs applied to the respective first and second input legs. The input legs may each be implemented as a weighted array of transistors, with each of the transistors in the weighted array associated with a given leg corresponding to a particular bit or other portion of an input signal applied to that leg. The non-complementary comparator may be used as a multi-digit comparator to determine the relative weight of digital words, or to implement other comparator circuits such as, e.g., majority rule circuits, analog common mode comparators, greater than/less than circuits, array addition and comparison circuits, serial adder-binary search (SA-BS) circuits, analog adders, add-compare-select (ACS) circuits, coupled memory cell comparators, and comparators with mask functions.

High-speed low-power low-offset hybrid comparator

Abstract: A comparator circuit includes a regenerative stage that uses a relatively small quiescent current combined with a relatively large dynamic current to charge a common-source node in the regenerative stage. The quiescent current helps maintain the common-source node in the regenerative stage near a desired charged level. The comparator circuit can also include an input isolation circuit to eliminate charge kick-back to the input signal lines.

High output swing comparator stage

Abstract: A circuit and method is provided that provides an amplification stage to a comparator device that matches transistor transconductances to provide adequate amplification and employs diode coupled transistors to control the common mode output bias voltage. The circuit and method provides for a high gain comparator stage with control over output common mode voltage, while providing rail to rail output swing during differential mode without an external feedback to the comparator device.

Method and circuit for checking lead defects in a two-wire bus system

Abstract: A method for checking lead defects in a two-wire bus system compares the voltage levels on the two wires with certain threshold values, with the comparison being made with the threshold values in the dominant and recessive states. A circuit for performing the method has one input of a first comparator connected with one wire, an input of a second comparator connected with the other wire, and the other inputs of the first and second comparators each being subjected to a voltage that is between the two voltage values on the wires in the dominant and recessive states in normal operation. One input of a third comparator also is connected with one wire, and one input of a fourth comparator is connected with the other wire, with the other inputs of the third and fourth comparators each being subjected to a voltage that is above the maximum voltage value on the wires in the dominant and recessive states during normal operation. The outputs of the first and second comparators are supplied to a subtractor, with a voltage adaptation at the level of the output signal taking place. The output signal of the subtractor is supplied to the input of a fifth comparator, and the output signal of the subtractor also is supplied through a diode to the input of a window comparator. The outputs of the third and fourth comparators also are connected with the input of the window comparator.

Integrated differential current comparator with input to output electrical isolation

Abstract: An isolated integrated differential current comparator for comparatively measuring the current passing through one or two resistors using a thermal difference sensor employing the Seebeck effect in an integrated circuit that is coupled to the resistors. The thermal difference sensor detects the temperature difference between the resistors, which is proportional to the square of the current passing through them. The output of the current comparator is electrically isolated from the inputs. The output is scalable and in circuit topologies requiring full signal isolation. The integrated differential current comparator is applicable to hot swap applications and applications where isolation of a number of signals is needed.

Noise suppression circuitry and method

Abstract: A circuit and method are disclosed for monitoring the voltage level of an electrical signal, such as an unregulated power supply. The circuit includes a comparator that compares the electrical to the voltage reference and generates an output having a value that is based upon the comparison. A oscillation suppression circuit receives the output of the comparator and generates an output signal that follows the output of the comparator once the output of the comparator remains stable and in the same logic state for a predetermined of time.

Oscillator averaging phase shift generator

Abstract: Two oscillators, such as in two pulse width modulator circuits of DC to DC power converters, are maintained in synchronization and at a predetermined phase shift from one another by a circuit incorporating a comparator. A sawtooth signal output from the master oscillator is fed to one comparator input while the sawtooth signal is filtered and applied to the second input of the comparator to generate an approximately 180° phase shift turn-on at the output of the comparator that is fed through a driver circuit to an input of a second oscillator. By insuring that the faster operating oscillator is the master, the slave oscillator will be triggered by the signal from the master.