Showing papers on "Current divider published in 2023"
TL;DR: In this article , the performance of a garlic harvester using the depth limit, straw divide, and straw lift modes was studied in Lanling County, Shandong Province, China, according to the characteristics of high hardness, good uprightness and narrow row spacing of garlic planting.
Abstract: The technology of the divider and lifter mechanisms of a garlic harvester using the depth limit, straw divide, and straw lift modes was studied in Lanling County, Shandong Province, China, according to the characteristics of high hardness, good uprightness and narrow row spacing of garlic planting. A test prototype of the divider and lifter mechanisms of the garlic harvester was designed and manufactured. Single-factor experiments and orthogonal regression experiments were carried out using the experimental factors of working speed, the angle of the divider, the height of the tip of the divider’s tooth from the ground, the ratio of the lifter’s speed to working speed and the length of the lifter’s tooth. The index was the success rate of feed. The results showed that the working speed, the angle of the divider and the length of the lifter’s tooth had a significant influence on the success rate of feed (p < 0.05), but the experimental factors of the height of the tip of the divider’s tooth from the ground and the ratio of the lifter’s speed to working speed did not have a significant influence on the success rate of feed (p > 0.05). The effects of the angle of the divider, the working speed, and the length of the divider’s tooth on the success rate of feed decreased in significance. When the working speed was 0.72 km·h−1, the length of the lifter’s tooth was 343.5 mm and the angle of the divider was 20°, the success rate of feed was the highest (98.18%). The research results are conducive to promoting high-quality and efficient combined harvesting of garlic in Lanling County, Shandong Province, China.
1 citations
TL;DR: In this article , a multi-mode frequency divider with modulus expansion is presented to address the issue of wrongly altering the divider ratio at the boundary of the moduli expansion when multimode dividers were utilized in fractional-N phase locked loops (PLLs).
Abstract: A method of moduli expansion was presented to address the issue of wrongly altering the divider ratio at the boundary of the modulus expansion when multi-mode dividers (MMD) were utilized in fractional-N phase locked loops (PLLs). The multi-mode frequency divider was designed as the cascade of the 2/3 frequency dividers with an RS control terminal. Compared to traditional methods, only one OR gate is required for each modulus expansion, reducing the chip area. The 2/3 divider was designed using a True Single-Phase Clocked (TSPC) D-trigger structure, and each D-trigger uses a logic control technique with clearing and setting the number. An eight-stage multi-mode frequency divider with modulus expansion was developed using SMIC 55 nm CMOS technology. The simulation results demonstrated the large frequency divider range of the multi-mode frequency divider and its ability to carry out consistent switching operations over the 8–511 frequency divider range. The power consumption is 66.04W at a supply voltage of 1V, an input frequency of 2GHz, and an output frequency of 250MHz.
13 Jun 2023
TL;DR: In this article , a power divider bearing the Wilkinson's name has been presented for WLAN applications with a design that includes three output ports and two lines with a length of L = λ/4 (quarter wave).
Abstract: – In microwave and radio frequency (RF) applications, the power divider is a well-known threeport device that is very essential. It can be used extensively in balanced power amplifiers, radar systems,and phase shifters. It is well-known that the power divider bearing Wilkinson's name is the most wellknown and respected of all power dividers.This divider uses a single frequency band and has two lines witha length of L= λ/4 (quarter wave). It operates on a single frequency f=c/λ.The primary function of these microwave devices is to establish a power distribution from an input signalto a predetermined number of output signals. This is a very important duty for these devices.This power divider that has been presented has a design that includes three output ports. Optimisation withthe help of the HFSS simulator will make it possible to have a power divider for applications related toWLAN (the band will cover WLAN at a frequency of 2.4 GHz).The standard Wilkinson power divider (WPD) may have a straightforward design, but despite its ease ofconstruction, it offers satisfactory performance despite its restricted bandwidth (isolation).
TL;DR: In this paper , a composite transmission line based reconfigurable power divider with high power division ratio, variable negative group delay, and lower characteristic impedance is presented in this work.
Abstract: This article presents the combined analysis of reconfigurable power division and negative group delay (NGD) in a power divider. A novel composite transmission line based reconfigurable power divider with high power division ratio, variable negative group delay, and lower characteristic impedance is presented in this work. The impedance transformation in composite transmission lines control both negative group delay and power division. This power divider possesses a wide range of power division ratios from 1 to 39, adequate isolation, impedance matching, and NGD of [Formula: see text] ns to [Formula: see text] ns in the reconfigurable transmission path. The negative group delay is achieved without using any additional group delay circuits. Theoretical equations corresponding to the low characteristic impedance of the transmission line sections and that of isolation elements are derived. The measurement results justify the attainment of high tuning of the power division ratio and negative group delay. Isolation and return loss are higher than - 15 dB at the centre frequency of 1.5 GHz. The significant contributions of this design can be listed as the wide reconfigurable power division along with negative group delay and reduced size.
23 Mar 2023
TL;DR: In this article , a composite transmission line (CT) based reconfigurable power divider with high power division ratio, variable negative group delay and lower characteristic impedance is presented in this work.
Abstract: Abstract This article presents the combined analysis of reconfigurable power division and Negative Group Delay (NGD) in a power divider. A novel composite transmission line (CT) based reconfigurable power divider with high power division ratio, variable negative group delay and lower characteristic impedance is presented in this work. The impedance transformation in composite transmission lines controls both NGD and power division. This power divider possesses a wide range of power division ratios from 1 to 39, adequate isolation, impedance matching, and NGD of-3.4 ns to-4.7 ns in the reconfigurable transmission path. The NGD is achieved without using any additional group delay circuits. Theoretical equations corresponding to the low characteristic impedance of the transmission line sections and that of isolation elements are derived. The measurement results justifies the attainment of high tuning of the power division ratio, and NGD. Isolation and return loss are higher than-15dB at the centre frequency of 1.5GHz. The major contributions of this design can be listed as the wide reconfigurable power division along with negative group delay and reduced size.
TL;DR: In this article , a radial sixteen-way power divider with a star-shaped microstrip isolation network is presented, where the radial slots are cut in the metal layer of the SIW, and isolation resistors are added.
Abstract: A substrate integrated waveguide (SIW) radial sixteen-way power divider is presented. This power divider adopts two layer substrates, one of which is used to design the radial power divider cavity of the SIW, and the other layer is used to design the star-shaped microstrip isolation network. To improve the isolation performance, radial slots are cut in the metal layer of the SIW, and isolation resistors are added. The step impedance probes ensure good matching of input and output ports. For verification, a SIW radial sixteen-way power divider is manufactured and measured. The measured result shows that the 15-dB input bandwidth and output bandwidth of the SIW sixteen-way power divider reaches 12.6% and 20.2% respectively, the insert loss (IL) is lower than 2 dB, and the isolation between the output ports is better than 15 dB.
TL;DR: In this paper , a comparative performance analysis of two quadrant CMOS analog divider with two quadrants CMOS approximation divider using 45nm technological node has been carried out.
Abstract: Abstract: Current mode Analog Dividers are widely used in various circuits such as fuzzy logic controllers, neural networks, adaptive filters and variable gain amplifiers. When these current analog divider circuits implemented in DSM technology, many of the second order effects starts deteriorating its performance. Most of the available literatures on analog dividers are reporting performance of these circuits implemented using long channel MOSFETs. Hence it is a peak time to compare the performance variation between various proposed analog circuits implemented in lower technological nodes. This is for identifying most reliable circuit which safely works in this node. .In this work a comparative performance analysis of two quadrant CMOS analog divider against two quadrant CMOS approximation divider using 45nm technological node has been carried out. The obtained result indicates that Approximation Divider is reliabie than two quadrant CMOS analog divider. The entire work is carried out using Tanner software.
TL;DR: In this paper , a balanced-to-balanced dual-band diplexing power divider (DBDPD) implemented on a new asymmetric series T-junction MS transition is proposed.
Abstract: In this brief, a balanced-to-balanced (BTB) dual-band diplexing power divider (DBDPD) implemented on a new asymmetric series T-junction MS transition is proposed. Firstly, a four-way BTB power divider (PD) as feed network was designed. The T-junction microstrip-slotline (MS) transitions are employed to realize phase shift and power division within a wide bandwidth. The balanced U-type MS transitions are adopted at each balanced port, which can realize superior common-mode (CM) suppression intrinsically while the differential-mode (DM) responses are independent. Then, the BTB DBDPD is realized by adding four pairs of step impedance resonators (SIRs) asymmetrically to the series T-junction. As a result, an asymmetric series T-junction MS transition with diplexing function is formed, which can flexibly adjust the operating passbands and adapt to the balanced port. Meanwhile, SIRs are employed to realize four sharp passbands. So as to verify the feasibility of the theoretical design, the proposed designs are manufactured. A good agreement can be observed between the simulation and measurement.
TL;DR: In this article , the authors derived analytical expressions for amplitude-frequency and phase-frequency characteristics of the broadband voltage divider with parallel-series connection of R-, C-elements of the high-voltage arm.
Abstract: Purpose. Determination in the analytical form of the maximum limiting influence of the non-identity of the resistive elements of the high-voltage arm on the amplitude-frequency characteristic and phase-frequency characteristic of the voltage divider with parallel-series connection of R-, C-elements of the high-voltage arm. Methodology. Based on the previously developed theory of broadband voltage dividers with parallel-series connection of R‑, C-elements, analytical expressions for amplitude-frequency and phase-frequency characteristics of the voltage divider are obtained and investigated taking into account the limit case of non-identical resistive elements of high-voltage arm. Results. The nature of the dependencies of the frequency characteristics of the broadband voltage divider on the value of the tolerance of the resistive elements of the high-voltage arm, the division factor of the voltage divider in a wide range of frequency changes are determined. Simplified approximating expressions for the maximum values of frequency characteristics of the voltage divider are proposed and their error is determined. Originality. For the first time in the analytical form the limiting influence of non-identity of resistive elements of a high-voltage arm of a voltage divider on its frequency characteristics is considered. A mathematical model of this influence is constructed and the limit values of frequency characteristics of the voltage divider are determined. Practical value. It is recommended to introduce into the normative documentation of broadband voltage dividers the corrected value of the division factor, which allows to significantly reduce the deviation of the actual value of the division factor of the voltage divider from the normalized value in a wide range of frequency changes.
20 Jun 2023
TL;DR: In this article , a 1 to 4 time-delay power divider was proposed to enhance the instantaneous bandwidth of a VICTS antenna with phase and amplitude relation between each port.
Abstract: In this paper a 1 to 4 time-delay power-divider was provided. The phase and amplitude relation between each port was simulated. The time-delay between the port was 0.016 ns in the x-direction and 0.16 ns in the x-direction. The maximum amplitude difference between each port was 1 dB and the maximum phase difference error was ±6°. The S11 value was lower than -20 dB. The proposed time delay power divider can be applied to VICTS antenna to enhance the instantaneous bandwidth.
16 Feb 2023
TL;DR: In this paper , a power divider with 55% overall compactness in size compared to the conventional Wilkinson power dividers using a defected microstrip structure was presented, and the proposed circuit is reciprocal and it divides and combines input power with less than 1 dB insertion loss.
Abstract: A power divider with 55% overall compactness in size compared to the conventional Wilkinson power divider is presented using a defected microstrip structure. The proposed circuit is reciprocal and it divides and combines input power with less than 1 dB insertion loss. This compact power divider/combiner demonstrates a wide operational fractional bandwidth of 83%. To the best of the authors’ knowledge, this is the best-reported compactness achieved in a power divider using only a defected microstrip structure.
TL;DR: In this article , a new wideband Wilkinson 16-way power divider on microstrip line operating at X-band (8-12GHz) using loaded slow-wave structure of spurline to accomplish miniaturization is presented.
Abstract: A New wideband Wilkinson 16-way power divider on microstrip line operating at X-band(8-12GHz) using loaded slow-wave structure of spurline to accomplish miniaturization is presented in this paper.The equations used for the 2-way power divider unit loaded with symmetrical single-spurline structures are based on the concept of spurline and odd-even modes using transmission line analysis.Then the 2-way power divider in X-band is cascaded to design 16-way power divider, while every cascade transmission line is loaded with symmetrical-spurline structure.The designed 16-way power divider has compact size of 197 mm × 55.1 mm × 6.808 mm including cavity and provides good impedence matching at all ports.Its return loss is better than 12.98dB, insertion loss is less than 15.1dB and isolation is better than 15dB across the 8 to 12GHz range, which is in good agreement with the simulation results.
TL;DR: In this article , an on-chip current-driven CMOS parametric frequency divider (PFD) that provides 2:1 frequency division with an output frequency of 2.4 GHz is presented.
Abstract: This paper introduces an on-chip current-driven CMOS parametric frequency divider (PFD) that provides 2:1 frequency division with an output frequency of 2.4 GHz. A custom input driver stage with a buffer enables to generate the input current of the PFD core from a digital clock signal or sinusoidal source, and a band-pass filter (BPF) stage suppresses undesirable harmonics at the output. Analyses and discussions of design considerations provide insights into the PFD’s input driving conditions, filtering characteristics of the output driver, as well as the effects of the limited quality (Q) factor of passive components and layout parasitics. A prototype chip was fabricated in standard 65-nm CMOS technology and tested. The minimum required supply voltage for the PFD driver is 1.4 V with an input frequency of 4.8 GHz, whereas the PFD has an operating frequency range from 4.5 GHz to 5.1 GHz with a supply voltage of 1.5 V. To the best of the authors’ knowledge, the proposed PFD is the first on-chip implementation of a current-driven parametric frequency divider in a standard CMOS process with sub-6 GHz operation, which demonstrates the feasibility of on-chip integration into RF systems.
TL;DR: In this paper , a tri-band filtering power divider with a pair of out-of-band transmission zeros is presented, which mainly consists of triband filter matching structures, transmission lines introducing transmission zero, and isolation resistors.
Abstract: In this brief, a novel tri-band filtering power divider with a pair of out-of-band transmission zeros is presented. It mainly consists of tri-band filter matching structures, transmission lines introducing transmission zeros, and isolation resistors. Through even- and odd-mode analyses, general design equations for the three parts can be derived separately. By applying coupled lines, the circuit size is further compact. For verification, a third-order tri-band filter PD working at three independent bands with a pair of out-of-band TZs θz = 60° is designed. Good agreement between the measured and simulated results is attained so as to successfully validate the correctness of the proposed design approach.
TL;DR: In this article , the basic design of a power divider with two symmetrical quarter-wavelength branches that provide matching conditions at all of its ports is the focus of the research.
Abstract: Abstract: The basic design of a power divider with two symmetrical quarter-wavelength branches that provide matching conditions at all of its ports is the focus of the research. Fr4 was chosen as the design's substrate, and 2.9 GHz is the operating frequency for the circuit. The structure of the power divider rules, which were derived from a circuit-theoretic analysis of AC power-flow expressions, reflects the topology and voltage profile of the network. We show how the power divider laws can be used to analyse power networks. The Wilkinson Power Divider has several uses, including feeding circuits for antenna arrays and measurementsystems