Showing papers on "Data transmission published in 1976"

Packet-switched data communications system

Abstract: A packet-switched digital data communication system operable in a store-and-forward mode is provided for enabling substantially simultaneous full-duplex communication between a plurality of telecommunications terminals, facsimile transceivers or other data input sources over a communications network with a plurality of other terminals, facsimile transceivers or other data sources having access to the communications network and with which such communication is desired. The disclosed packetizing of data and transmission thereof in a store-and-forward mode with dynamic routing provides a highly efficient utilization of the transmission facilities, substantially error-free data transmission and a handshake capability between a wide variety of dissimilar and otherwise incompatible terminal devices such as facsimile transceivers having differing protocols, modulation techniques and other speed and code characteristics. Large blocks of data and other message information from data terminals are subdivided into data packets prior to transmission, converted into a systemwide compatible protocol, compressed, transmitted independently, time multiplexed with other packetized data from other terminals on the communications network, stored and forwarded on a priority basis and in accordance with network availability at one or more switching nodes in the network, reassembled from the received packets at a destination processor into the original data messages for coupling to the message destination terminals such that the received message is decompressed and reconverted into a format compatible with the destination terminal characteristics to enable information interchange therebetween.

A New Digital Echo Canceler for Two-Wire Full-Duplex Data Transmission

Abstract: A new approach to echo canceling for two-wire fullduplex data transmission is proposed. The canceling signal is directly synthesized from the binary data, using a transversal filter approach, and the usual multiplications are replaced by additions and subtractions, thus allowing efficient operation of a large number of taps as required for the canceling of distant echoes. As a specific application, a system processing one sample per baud is discussed where timing signals at both communicating stations are assumed to be synchronized. A stochastic adjustment gradient-type algorithm is used for both training and adaptive tracking of the canceler. It is shown that convergence does not depend on intersymbol interference, timing phase, carrier phase, or the energy ratio of the local to the received signal, but is a function only of the number of taps. Convergence time is proportional to that number, and the optimum step size for fastest convergence is equal to the reciprocal of the number of taps. The residual fluctuation noise is proportional to that part of the mean-square (MS) error which cannot be reduced by the canceler and is a simple function of the product of the tap signal and the step size. The predicted convergence properties are verified by simulation results. Finally, it is shown how such an echo canceler might be used to allow two-wire full-duplex transmission for data rates as high as 4800 bit/s.

Packet-switched facsimile communications system

Abstract: A packet-switched facsimile communication system operable in a store-and-forward mode is provided for enabling substantially simultaneous full-duplex communication between a plurality of telecommunications terminals, such as facsimile transceivers, over a communications network with a plurality of other facsimile transceivers having access to the communications network and with which such communication is desired The disclosed packetizing of data and transmission thereof in a store-and-forward mode with dynamic routing provides a highly efficient utilization of the transmission facilities, substantially error-free data transmission and a handshake capability between a wide variety of dissimilar and otherwise incompatible facsimile machines having differing protocols, modulation techniques and other speed and code characteristics Large blocks of data and other message information from facsimile data terminals are subdivided into data packets prior to transmission, converted into a systemwide compatible protocol, compressed, transmitted independently and time multiplexed with other packetized data from other terminals on the communications network, stored and forwarded on a priority basis and in accordance with network availability at one or more switching nodes in the network, reassembled from the received packets at a destination processor into the original data messages for coupling to the message destination terminals such that the received message is decompressed and reconverted into a format compatible with the destination terminal characteristics to enable information interchange therebetween

Optical Pulse Formats for Fiber Optic Digital Communications

Abstract: Some new optical pulse formats are investigated for solving practical problems in fiber optic communication systems. These pulse formats provide many advantageous features such as error monitoring capability, abundant timing information, uniform optical power utilization, stable detection of optical input, and so forth. It is shown that a modification of Personick's receiver design theory can be used for comparison of various optical pulse formats. The comparison suggests that for state-of-the-art fiber systems with moderate fiber loss and moderate repeater spacing, where no pulse equalization is required, some new classes of 1 binary digit converted to 2 binary digits (1B2B) or 2B3B formats will permit the realization of very simple and reliable repeaters for fiber optic digital transmission. A future low-loss fiber system may permit a very long repeater spacing with the help of equalization. In this case, application of the correlative signal-processing technique is shown to be very promising. Experimental 6.3 Mbit/s and 100 Mbit/s transmissions demonstrate some advantageous features of these optical pulse formats.

Synchronization technique for data transfers over an asynchronous common bus network coupling data processing apparatus

Abstract: Data transfer synchronization is achieved in a data processing system by a transferring unit enabling a clock cycle stall mechanism each time a transfer is attempted, disabling such mechanism upon receipt of a predetermined response from the receiving unit, the mechanism actually producing a clock cycle stall if such predetermined response is delayed beyond the duration of the clock cycle. Further, such stall mechanism is enabled in a receiving unit before the expected receipt of information, and actually produces a clock cycle stall if such response is so delayed.

Multiplexer for a distributed input/out controller system

Abstract: A distributed input/output system is disclosed for controlling numerous peripheral devices and the transfer of data signals and control signals between those devices and a general purpose digital computer. The control system described includes a multiplexer which can accommodate as many as eight input/output devices under the control of separate programmable microcoded peripheral-unit controllers. Each controller is adapted to be located at or on an individual peripheral device and each is connected to the multiplexer by an identical ribbon cable that is employed to cary both signals and power. Each controller employs a substantially identical microengine, that is, a microcoded processor, currently of five integrated circuit chips. The peripheral-unit controllers may be configured somewhat differently depending upon whether the peripheral device utilizes data signals in parallel or in series. Data may be transferred directly between a computer memory unit and the peripheral devices without requiring the use of any computer working registers and without requiring subroutines to preserve an ongoing main program. Each peripheral-device controller can issue interrupt signals which are processed by the computer on a priority basis when they occur simultaneously. Some microengines employ two sets of programmed microcodes and each set is selectable by a switch, such as a wire jumper, for controlling either of two different kinds of devices. The multiplexer of this invention includes circuits for forcing the truth value of a selected data signal to a predetermined level and for recognizing a particular data term for terminating data transfer operations. These capabilities are especially useful for data signals that include a parity bit and for data signals that represent an alphanumeric character.

Dual speed full duplex data transmission

Abstract: A dual-speed, dual format full-duplex two-wire voiceband data transmission system provides automatic speed selection at the answering terminal responsive to a handshaking sequence which is compatible with existing systems operating at telegraph speeds. Existing systems provide asynchronous full-duplex serial data transmission in the speed range of zero to 300 bits per second using frequency-shift keying of tones in split frequency bands dedicated to the respective transmisson directions. Alternative full-duplex serial data transmission at 1200 bits per second using phase-shift keying of carrier waves in these same split frequency bands can now be provided from a common line protocol.

Data transfer control apparatus and method

Abstract: An improved data transfer apparatus and method is fabricated by multiplexing at least a portion of the address of the peripherals on the data bus. Data transfer is simplified by adopting identical control timing for the read and write cycles, setting up address and data information early within a cycle and synchronizing the output of such information on the output busses coupled to the peripherals. Data transfer control signals may be encoded to simplify read and write input/output and memory operations. The advantage of such improvements permits reduce component count, pin requirements and gives rise to an ability to incorporate more system functions on a single chip.

Seismic data telemetering system

Abstract: A plurality of data acquisition and transceiver units are connected in series to a central signal processor through a common telemeter link. The telemeter link includes a data channel, an interrogation channel and a control channel. The signal propagation velocity through the control channel may, for example, be greater than the signal propagation velocity through the interrogation channel. The central signal processor sends an interrogation signal through the interrogation channel to the data acquisition units. After a selected delay, a control pulse is transmitted. The delay between transmissions of the two signals is proportional to the differential travel time of the signals in the two channels. Accordingly the signal through the control channel will overtake and intercept the signal propagating through the interrogation channel, at a selected data acquisition unit. When any selected data acquisition unit receives a control signal through the control channel at the same time that it receives an interrogation signal through the interrogation channel, that unit is activated and a desired function is performed. The control signal is a square wave pulse having a width which is adjustable by integral multiples of the differential travel time. By adjusting the width and transmission-time delay of the control pulse, any selected subset of one or more consecutive units may be activated. Each data acquisition unit may have two or more input channels, which are connected in turn through common electronics to the data transmission channel by means of a channel selector or multiplexer. The interrogation signal may exist in one of two or more states. In the first state, in combination with a control pulse, the interrogation signal resets the multiplexer. In the second state, the interrogation signal advances the multiplexer to the next input channel in sequence.

Computer to computer communication system

Abstract: A computer to computer data communication system for minimizing software protocol is disclosed wherein transmitted errors in data transmitted from one computer to another are detected when they occur by means of a bit-by-bit data echo transmission technique. True and inverted or complementary data are transmitted simultaneously serially over twisted pair lines for comparison, bit-by-bit by comparing each transmitted bit to the corresponding inverted bit to derive an error signal indicative of the condition of like polarity of the compared bits. If the compared bits are of like polarity, an error signal is generated to enable correction of the transmission error on a word by word basis, while inhibiting processing of the uncorrected data. Concurrently, received data is returned to the transmitting processor over a return data line for a like comparison. When an error condition exists, the returned data is inverted, forcing an error condition and inhibiting further transmission for the remainder of the transfer cycle. Thus, bit-by-bit detection, word-by-word correction and a variable block length capability in a double data transfer environment are accomplished, with both data processing and transmission inhibited until data errors are corrected.

Method and system for selectively accessing multiplexed data transmission network for monitoring and testing of the network

Abstract: A method and system for accessing data in a time division multiplex communication network at the multiplexed level without disturbing the transmission of the data. A multiplexed data stream containing a predetermined pattern of framing signals and subscriber data from a plurality of subscriber channels is accessed directly by line accessing means located in the transmission path of the data stream. The line accessing means does not disturb the transmission of the multiplexed data stream, i.e., allows the multiplexed data stream to pass through the line accessing means, but provides a monitored data signal having the same data content as the multiplexed data stream, thereby essentially providing undisturbed direct access to the multiplexed data stream. A control signal designating one of the plurality of subscriber channels as the desired subscriber channel is generated, and framing signals in the multiplexed data stream are detected. The detected framing signals and the generated control signal are utilized to locate the designated one of the plurality of subscriber channels in the monitored multiplexed data stream for monitoring, testing or for use of the data contained in the located channel. Specifically, the located one of the plurality of subscriber channels is monitored so its data framing and content can be observed. For testing purposes, various codes such as a loopback code or a multipoint junction code may be inserted in the designated one of the plurality of subscriber channels in the multiplexed data stream without demultiplexing the data stream or otherwise disturbing the transmission of the stream. In this manner, loopbacks at various points in the system can be effected and test codes such as a pseudo-random code may be transmitted through the loopback and monitored for errors.

Joint adaptive echo canceller and equalizer for two- wire full-duplex data transmission

Abstract: An adaptive equalizer and echo canceller jointly respond to a common error difference between the actual output and the quantized digital output of a data receiver in a two-wire digital data transmission system to achieve simultaneous full-bandwith full-duplex operation. Two-wire transmission channels are typically terminated in hybrid balancing networks which because of their fixed impedances permit "echoes" of the transmitted signal to interfere with reception of the much weaker incoming signal. Both the equalizer and canceller are adaptively adjustable transversal structures.

Sensor data input by means of analog to pulse width-to digital converter

Abstract: A system for transmitting data from remote sensors to a digital processing system is disclosed herein. The analog sensor output is converted to pulse width signals at the sensor location and converted from pulse width to digital data at the digital processor. Delay circuits at each sensor location permits the use of a single interrogation signal to simultaneously interrogate each sensor. The generation of the pulse width signal is delayed at each sensor location so that the pulse width signals from the sensors are serially received at the pulse width to digital converter. Only a single data transmission line is required for transmitting the interrogation signal and the pulse width signals back and forth between the digital processor and the sensor locations. In one embodiment, energy storage means are provided at each sensor location which provides sufficient electrical power for the operation of the sensor and the analog to pulse width converter. This energy storage means is charged by the interrogation signal transmitted along the single data transmission line eliminating the need for providing individual power leads at each sensor location.

System and method for increasing the output data throughput of a computer

Abstract: A circuit and method for increasing the output data per unit time from a computer to its associated peripheral terminals or utilization devices is disclosed in which the computer output address and data lines are time multiplexed by a novel decoding technique which enables the address bits and data bits to be interpreted together to form a new data word having a number of bits equal to the sum of the original data bits and the address bits interpreted as data bits. A plurality of decoders, each at a peripheral terminal and each having an identification address code, enable a window for decoding multiple transfers of data on output address and data lines, said window having a predetermined time duration during which all other peripheral identification address codes are locked out, until the data transfer is completed. A microprocessor embodying the invention is also disclosed in which the output data capability is increased from eight to sixteen bits without hardware modification to the microprocessor.

Time diversity data transmission apparatus

Abstract: An asynchronous, time diversity transmission apparatus including a data encoder at a transmitting location and an error-correcting data decoder at a receiving location for overcoming the effects of signal fading, impulsive noise and interference. The asynchronous data encoder encodes a single input data stream into three or more redundant, parallel data outputs having time diversity introduced by successive delays. The data outputs are frequency multiplexed and propagated over a transmission circuit. Received data is demultiplexed and input to the data decoder where it is processed to remove the time diversity. Three or more outputs from the decoder are combined to form a single, error-corrected data output.

Priority network for devices coupled by a common bus

Abstract: A priority network utilizing a common bus coupled to a plurality of priority seeking peripheral devices wherein a processor or any number of processors is connected to the common bus. Each successive peripheral device is connected to the common bus in increasing priority order, such that each device will have a unique priority defined. Each peripheral device is provided with an associated peripheral control unit. Each of the peripheral control units is connected in serial fashion on an enabling line with the output of the higher priority control unit providing an enabling input to the next lowest priority peripheral control unit, such that the highest priority device requesting bus access prevents all lower priority devices from gaining access to the common bus until the higher priority device has completed its data transfer.

Testing and switching system including remotely controllable stations for information transmission and communications networks and systems

Abstract: A testing and switching (tester) system is disclosed for information transmission and communications networks and systems and the like. According to a preferred embodiment, a data transmission network is advantageously of the type in which remotely located users or customers are afforded time-shared access to a centrally located computer. The data transmission network includes remotely located switching stations which are linked to the central computer over data transmission lines which include selectively actuated normal and fallback local loops. The network users gain access to the centrally located computer over selectively actuated local lines to the remotely located switching stations. The tester system comprises switching and testing apparatus which includes a programmable tester computer located at the remotely located stations and preferably at the centrally located computer site also. The tester computer is programmable from the centrally located computer site and is preferably under command control of the centrally located computer site. The tester system tests, including programmed and manual tests, network data transmission parameters at sites having switching and testing apparatus, and also performs programmed and manually controlled switching at those sites. The tester system is especially suited to testing and switching in a telephone data transmission network in which the data transmission lines are typically leased data transmission long lines and in which the selectively actuated local lines to the remotely located stations are part of the telephone company DDD network. Access to the remotely located stations by the centrally located computer site is also gained over selectively actuated lines which advantageously form part of the DDD network. The tester system advantageously tests and measures voice and data transmission parameters including signal level, phase jitter, and noise. Methods and apparatus are also disclosed for performing these tests.

Digital controller system

Abstract: A digital controller system for controlling the flow of a plurality of processes, each of the processes being provided with a process detector and an actuator, the digital controller system comprising: a digital bus for transmitting digital signals from one location to another; an analog bus for transmitting analog signals from one location to another; a plurality of direct digital loop stations, each of said direct digital loop station adapted to be connected to a process detector and an actuator of a process for receiving analog signals characterizing the state of the process from the process detector and transmitting the analog signals onto the analog bus and for receiving digital signals controlling the flow of the process from the digital bus and transmitting corresponding analog signals to the operating apparatus; and a central processor unit for transmitting the digital signals controlling the flow of the process to the digital bus, and for receiving the analog signals characterizing the state of the process from the analog bus, the central processor unit including a digital computer, an analog-to-digital converter and a data transmission unit.

Three-level serial digital data communication system

Abstract: A three-level, direct-coupled binary serial digital data transmission channel using a shielded twisted wire cable as the transmission line. The binary data to be transmitted is encoded into a self-clocking three-level code requiring only one transition for each bit transmitted. A balanced direct-coupled three-state differential driving circuit is used as the transmission line driver, and a balanced, direct-coupled three-level differential receiver circuit is used as the transmission line receiver.

Receivers for pulses of different widths

Abstract: A data transmission system for transmitting data and subsidiary information by means of pulses of different widths corresponding to a multiple of a signal propagation time delay of a NAND gate. The system makes it possible to simplify the construction of the data transmission device to a considerable degree and at the same time to transmit data at a high speed, and includes a variety of circuits for generation and demodulation of the pulses.

Multi-channel multiplex data transmission system

Abstract: The sum and difference signals of a pair of data channels are applied to a pair of roll-off filters, respectively. The outputs of said roll-off filters are modulated by a pair of carrier signals which have the phase difference (π/2) to each other. The modulated signals are added to each other in an adder and a single output signal is provided from the output of said adder. Said output signal and another output signal relating to another pair of data channels, and some pilot signals are applied to an adder, the output of which is transmitted to a receiving station in the form of a multi-channel multiplex data signal. At the receiving station, the received signal is demodulated with the inverse process of the above modulation steps and the demodulated data signals are applied to an automatic equalizer. The present invention described above provides high speed data transmission through a narrow-band-line which has only almost the Nyquist band width.

Automatic switching unit for data communications network

Abstract: An automatic switching unit for connection to a modem at a remote site in a data communications network. The switching unit normally connects the modem to a primary data transmission path. If the primary path malfunctions, a central site operator can telephone the remote site and establish a secondary data transmission path. The switching unit answers the incoming calls and automatically disconnects the modem from the primary data transmission path. Once the primary data transmission path has been repaired, the central site operator causes the switching unit to return communications to the primary data transmission path. In one embodiment, this transfer can be made while maintaining communications over the secondary data transmission path.

Evaluation of Decision Feedback Equalization and Viterbi Algorithm Detection for Voiceband Data Transmission--Part II

Abstract: This paper describes experimental results of simulated 12000 and 14400 bits/s quadrature amplitude-modulated (QAM) systems (which were described in detail in Part I [1] ) operating on real and simulated voiceband channels. These experimental results show that both Viterbi algorithm detection and decision feedback equalization allow digital data transmission at symbol rates exceeding the nominal bandwidth capabilities of typical telephone channels. It is demonstrated in these experiments that the Viterbi algorithm receiver structure tested is less affected by linear distortion than the decision feedback receiver but exhibits greater sensitivity to phase jitter. On conditioned voiceband channels where there may be substantial phase jitter, a reasonable compromise between sensitivity to distortion and noise and sensitivity to phase jitter is made by a modem employing decision feedback equalization and decision-directed carrier phase tracking.

Fault locating apparatus for digital transmission system

Abstract: Defective repeaters in a multihop, digital microwave transmission system are located by the use of a special test pattern which is generated at the transmitting terminal. At each repeater station, the two outputs of the phase demodulator are compared to determine if the test pattern has been properly received from the upstream repeaters. The special test pattern, S, has the characteristic that S = S(2N); that is to say, the test pattern equals the complement of itself delayed by 2N symbols. This special characteristic makes it unnecessary to employ a differential decoder in the test apparatus at each repeater station.

Data transmission system using analog to pulse width to digital conversion

Abstract: A data transmission system using analog to pulse width to digital conversion for transmitting data generated by an analog sensor to a digital processor is disclosed. A data request signal generated by the digital processor is gated by a processor interface circuit along a single wire data transmission line to a remote sensor activating both the sensor and its associated interface electronics. The data request signal also provides electrical power to the sensor and sensor interface electronics eliminating the need for separate electrical power leads. The sensor interface electronics after a period of time determined by the value of the analog signal generated by the sensor generates a low impedance to ground signal on the data transmission line. The low impedance to ground signal is detected by the processor interface circuit which terminates the transmission of the data request signal. The processor interface circuit further includes a pulse width to digital converter generating digital data indicative of the duration the data request signal is transmitted. More than one sensor may interface the single data transmission line and each sensor interface may be individually activated by interrogation signals generated by the digital processor.

Testing of digital systems

Abstract: A digital subscriber loop transmission system is disclosed through which a number of remote subscribers are serviced with a smaller number of time division channels. The digital transmission system includes an automatic channel testing unit which selects digital channels one at a time and in sequence for a series of automatic tests. Channels which fail these tests are withdrawn from service. One such test involves ringing and automatic number identification circuits by means of which subscribers' telephones are rung and the off-hook subscriber on a two-party line is identified, both by the use of supervisory codes in the digital pulse stream. These supervisory codes are used to test the supervisory circuits themselves and, incidentally, large portions of the overall system.

Transversal Filter Design and Application in Satellite Communications

Abstract: A brief literature survey of transversal filters is followed by a design example of a binary transversal filter. A particular application in the modulator of the single channel per carrier data transmission equipment is described. Computer simulations and COS/MOS hardware implementation proved the validity and the feasibility of the theory described by Mueller. Design and evaluation of a linear phase filter approaching the Nyquist channel is the end result of our study.

Centralized monitoring system for gas leakage

Abstract: A centralized monitoring system for gas leakage in which a plurality of remote terminal units are connected by a loop line and each remote terminal units is further connected to one or a plurality of gas leakage detectors which produce analog signals representing the degree of gas concentration. Each remote terminal unit converts the analog signals from the gas leakage detectors into digitally coded block data and then transmit the block data together with an address code in time division fashion to a central monitoring station also connected to the loop line for processing the block data to provide display of the status of the gas concentration at the central station. In the transmission of the data through the loop line, a double transmission check system and a loop line switching means are employed to achieve reliable and fast data transmission.