Showing papers on "Divisor published in 1993"

Exponential sums and lattice points III

Abstract: The Gauss circle problem and the Dirichlet divisor problem are special cases of the problem of counting the points of the integer lattice in a planar domain bounded by a piecewise smooth curve. In the Bombieri?Iwaniec?Mozzochi exponential sums method we must count the number of pairs of arcs of the boundary curve which can be brought into coincidence by an automorphism of the integer lattice. These coincidences are parametrised by integer points close to certain plane curves, the resonance curves. This paper sets up an iteration step from a strong hypothesis about integer points close to curves to a bound for the discrepancy, the number of integer points minus the area, as in the latest work on single exponential sums. The Bombieri?Iwaniec?Mozzochi method itself gives bounds for the number of integer points close to a curve in part of the required range, and it can in principle be used iteratively. We use a bound obtained by Swinnerton-Dyer's approximation determinant method. In the discrepancy estimate $O(R^K (\log R)^{\Lambda })$ in terms of the maximum radius of curvature $R$, we reduce $K$ from 2/3 (classical) and 46/73 (paper II in this series) to 131/208. The corresponding exponent in the Dirichlet divisor problem becomes $K/2 = 131/416$.

Mechanism and method for integer divide involving pre-alignment of the divisor relative to the dividend

Abstract: A mechanism for dividing an integer dividend by an integer divisor to generate an integer quotient operates by aligning the divisor relative to the dividend such that a right-most bit of the divisor is aligned with a bit M of the dividend. The divisor is compared to an integer value whose right-most bits are equal to bits of the dividend which are aligned with bits of the divisor. As a result of this comparison, quotient bits which positionally correspond to the dividend bit M and to bits of the dividend which are located to the left of the dividend bit M are cleared to zero. Also as a result of the comparison, the dividend is divided by the divisor as aligned relative to the dividend to thereby generate values for any uncleared quotient bits.

Iterative division apparatus, system and method employing left most one's detection and left most one's detection with exclusive OR

Abstract: This invention is an iterative technique for division. The divisor has N bits and the numerator has more than N bits, generally 2N bits. Each iteration includes initial detection of the position of a left most one bit (1011, 1035) of N most significant bits of the numerator. If this L is not zero, then the numerator in left shifted by L places (1016, 1039), the next L quotient bits are set to zero and the number of completed iterations of the division is incremented by L. An alternative embodiment detects bit position of the left most one of an exclusive OR of the N most significant bits of the numerator and the divisor. If this is nonzero, then the numerator shifts this number of places and the corresponding quotient bits are set to "0". Next the division technique calculates the difference between the N most significant bits of the numerator and the divisor. If the difference is greater than or equal to zero, then the next quotient bit is "1". If the difference is less than zero, then the next quotient bit is "0". The difference is substituted for the N most significant bits of the numerator, if this difference was greater than or equal to zero. Then the numerator is left shifted one place. These iterations repeat until the number of iterations exceeds N. Then the quotient is completely formed and the data of the last numerator is the remainder of the division. This technique eliminates useless data manipulation for the cases where this technique determines the quotient bits are "0". Using pre- and post-processing this technique can be used with signed numbers. In the preferred embodiment of this invention, the division logic is embodied in at least one digital image/graphics processor as a part of a multiprocessor formed in a single integrated circuit used in image processing.

On the greatest common divisor of polynomials which depend on a parameter

Abstract: The following computer algebra problem is considered : how to compute the gcd of the polynomials U(X, a) and V(Z, a) for various values of the parameter a? This problem appears, for example, in solving systems of algebraic equations by the elimination methods ~aer53], in computing the logarithmic part of the integral of a rational function [Trag76, Laz&Rio90], in solving difference and differential equations [Abr89], in summing rational functions [Abr71, Abr75, Gosp78], etc... A fast algorithm to solve this problem is described, and some applications of this algorithm are discussed.

Arithmetic functions associated with the infinitary divisors of an integer

Abstract: The infinitary divisors of a natural number n are the products of its divisors of the form pu2, where pV is a prime-power component of n and ya2 (where ya 0 or 1) is the binary representation of y. In this paper, we investigate the infinitary analogues of such familiar number theoretic functions as the divisor sum function, Euler's phi function and the Mbbius function.

Frequency divider circuit

Abstract: A programmable divide-by-N or divide-by-N+1/2 circuit is responsive to an input clock signal and to a plurality of binary-coded data signals corresponding to the divisor for providing an output clock signal having a frequency which is the frequency of the input clock signal divided by the value encoded on the data signals. The circuit includes two separate down counters 10, 12--one decrementing on the positive-going edge of the input clock signal and the other decrementing on the negative-going edge of the input clock signal. If the divisor is an integer N, the negative-clocked circuitry 12 is disabled and the positive-clocked circuit 10 counts down from N to 1 continuously. If the divisor is N+1/2, both counter circuits are used. In this case, both counters are preset with the value N, the positive-edge-triggered counter 10 decrements from N to zero while the negative-edge-triggered counter 12 decrements from N to one. Then, both are preset with the value N, and this time the positive-edge-triggered counter 10 decrements to one while the negative-edge-triggered counter 12 decrements to zero. This count swapping occurs continuously. The resulting output signals are combined in a shaping circuit 14 to produce a frequency-divided output signal having a preselected low-state pulse width.

Greatest common divisors and least common multiples of graphs

Abstract: A graphH divides a graphG, writtenH|G, ifG isH-decomposable. A graphG without isolated vertices is a greatest common divisor of two graphsG1 andG2 ifG is a graph of maximum size for whichG|G1 andG|G2, while a graphH without isolated vertices is a least common multiple ofG1 andG2 ifH is a graph of minimum size for whichG1|H andG2|H. It is shown that every two nonempty graphs have a greatest common divisor and least common multiple. It is also shown that the ratio of the product of the sizes of a greatest common divisor and least common multiple ofG1 andG2 to the product of their sizes can be arbitrarily large or arbitrarily small. Sizes of least common multiples of various pairsG1,G2 of graphs are determined, including when one ofG1 andG2 is a cycle of even length and the other is a star.

Divide circuit having high-speed operating capability

Abstract: A divide circuit which is adapted to obtain a quotient by using a dividend and a divisor, the dividend and the divisor being input signals of either quadruple logic or quadruple logic converted from binary logic, includes a unit for setting a candidate value of the quotient, a unit connected to the setting unit for multiplying the quotient candidate value by the divisor, and a unit connected to the multiplying unit for comparing a result obtained by the multiplying unit with the dividend.

Binary/decimal converter

Abstract: PURPOSE:To provide the binary/decimal converter capable of speedily converting binary (integral/decimal) data into decimal data by adding a little hardware to the conventional divider. CONSTITUTION:In making a decimal conversion of binary integral data, the 10 data according to the digits of the decimal data are inputted by a divisor selector 7 instead of a divisor to the divisor data input section of a subtraction shift type divider 3 capable of performing the normal division. In short, at the normal division operation, a dividend stored in a dividend register 1 is divided by the divisor stored in the divisor register 2. At the binary/decimal conversion, the binary integral data stored in the dividend register 1 is divided by the 10 data outputted in parallel from a 10 data generator 4. The 4-bit quotient is generated according to each digit to be stored in a quotient register 5. Like the one division processing, the binary/decimal conversion can be realized.

Picard groups of Hilbert schemes of curves

Abstract: We calculate the Picard group, over the integers, of the Hilbert scheme of smooth, irreducible, non-degenerate curves of degree $d$and genus $g \geq 4$ in ${\Bbb P}^r$, in the case when $d \geq 2g+1 $ and $r \leq d-g$ We express the classes of the generators in terms of some ``natural'' divisor classes

Gaps between consecutive divisors of factorials

Abstract: Given a positive integer TV, let r = r(N) be its number of divisors, denoted by 1 = c?i < d'2 < . . . < dr = N . Erdos [3] has defined a family of arithmetic functions (i) ^(^-Ef^-)^ ^^ i=i ^ ai ^ and conjectured that liminfF^An < oo, e > 0. N^oo (See also [4] for related results and problems.) The conjecture was proved by Vose [9], who was able to construct a sequence (A^)^^ such that (2) F,(^)=0,(l). It is clear that to obtain small values for F^{N) one needs numbers N with \"many\" divisors. In fact, the sequence (A^) constructed by Vose is a divisor sequence, i.e., TVjA^+i for each n. This was anticipated in [2] and [3], where Erdos specifically suggested the sequences

System for recording and reproducing data of optical disk

Abstract: PURPOSE:To prevent the occurence of a correction line being incorrigible with- out adding a hardware and to improve correction ability viewing in sector. CONSTITUTION:The data length of one data group unit is set as (n) by a prescribed format. An interleave length is regarded as (m) and the data is stored so that (m) pieces of error correction lines are formed in a data memory at the time of recording and reproducing the data. Further, the data length (n) and/or the interleave length (m) are set so that the interleave length (m) or the divisor of (m) becomes a value indivisible for the data length (n) in one data group.

Adjoint linear systems on a surface of general type in positive characteristic

Abstract: Let X be a minimal surface of general type defined over an algebraically closed field of positive characteristic p. For a given divisor D, we consider the spannedness properties of adjoint linear systems |K+D| on X. Under some numerical conditions on p and D, the failure of spannedness of |K+D| implies the existence of divisors with special properties. This leads to the following result: Let L be an ample line bundle and assume p > 5. Then |m(K+L)| is base point free for m > 2 and very ample for m > 3. Our proof is based on a technique of Shepherd-Barron using unstable vector bundles

Compression and decoding system for ascending-order integer string data

Abstract: PURPOSE:To shorten the processing time by decreasing the calculation quantity in the compression and decoding of the ascending-order integer string data. CONSTITUTION:The ascending-order integer string data D1 are divided by a divisor part 12 and the obtained quotient is compared by a quotient storage and comparison part 14 with old quotients which are obtained so far; only when the quotient is varied, the difference and remainder of the quotient are preserved as a compressed string D2 and when not, only the remainder is preserved. The quantity of data is decreased by the division, so the processing time for the compression and decoding is shortened. Further, since parameters required for the whole data are not necessary, the data can be added and deleted.

Average order of the divisor functions with negative power weight

Abstract: and we also study the averages of associated error terms. Throughout the paper, we shall refer to [6] as I and whose results we cite e.g. as I-Theorem 1. First we consider the case O^a-teZ, where Z denotes the set of all rational integers, and prove Theorem 1 which generalizes and in some cases corrects MacLeod's Theorem 8[8]. This case is easier to handle although the needed calculations are rather long. And the special case a = l of this is the starting point of the investigation of the case a3 as well, only for t―

Non-trivial Linear Systems on Smooth Plane Curves

Abstract: Let $C$ be a smooth plane curve of degree $d$ defined over an algebraically closed field $k$. A base point free complete very special linear system $g^r_n$ on $C$ is trivial if there exists an integer $m\ge 0$ and an effective divisor $E$ on $C$ of degree $md-n$ such that $g^r_n=|mg^2_d-E|$ and $r=(m^2+3m)/2-(md-n)$. In this paper, we prove the following: Theorem Let $g^r_n$ be a base point free very special non-trivial complete linear system on $C$. Write $r=(x+1)(x+2)/2-b$ with $x, b$ integers satisfying $x\ge 1, 0\le b \le x$. Then $n\ge n(r):=(d-3)(x+3)-b$. Moreover, this inequality is best possible.

Weights of Primitive Binary Cyclic Codes from Non-Primitive Codes

Abstract: Let s, k, integers such that s is a divisor of 2k−1 Let g(x) be a primitive divisor of xs −1 over F 2, and let π(x) be a primitive polynomial of degree k over F 2 We consider N the binary cyclic code C of length N = 2k −1, generated by For special cases, we determine the weights of C by using the weights of the irreducible cyclic code of length s, generated by

Performing integer and floating point division using a single SRT divider

Abstract: A method and apparatus for performing integer and floating-point divide operations using a single modified SRT divider 30 in a data processor 10. The floating-point and integer division is performed using SRT division on normalized positive mantissas (divided and divisor). Integer division shares portions of the floating point circuitry, however, the sequence of operations is modified during the performance of an integer divide operation. The SRT divider 30 performs a sequence of operations before and after an iteration loop to re-configure an integer divisor and dividend into a data path representation which the SRT algorithm requires for floating-point mantissas. During the iteration loop, quotient bits are selected and used to generate intermediate partial remainders. The quotient bits are also input to quotient registers 66 which accumulate the final quotient mantissa. A full mantissa adder is used to generate a final remainder.

Radix division of binary numbers in data processing system - subjecting divisor to reduction process followed by comparison process to generate part quotients

Abstract: The processing system operates on a dividend and divisor multi-digit values (DOR,DIV), to predict the quotient value. The division circuit operates to a known high radix division process, whereby each cycle results in a quotient bit, with the number of bits dependent upon the radix (r). The divisor and dividend values are stored in a register (DDR) and in shortened values are held in a separate register (DORM). Values with reduced length are subjected to a comparison to generate correct part quotient values forming the result. ADVANTAGE - Allows part quotients to be generated with minimum number of operators.

Process for finding the reciprocal of a divisor by stepwise approximation

Abstract: A novel process and a pure hardware and architecturally symmetrical division circuit is described which recursively and bidirectionally finds a quotient from a dividend and a divisor by approximation. It is thus possible to start the calculation with the highest or lowest position value or at the same time with the two extremes of the divisor/divident/quotient, in a parallel process. The division circuit therefore consists of four parts, with two symmetrical pairs. The left-hand main circuit (1), which is symmetrical with the right-hand sub-circuit (3), processes the divisor and, via the two control signals D/I and AS, controls the left hand sub-circuit (2) which is symmetrical with the right-hand sub-circuit (4) and processes the dividend in order to find the quotient. The two symmetrical parts can operate mutually independently, i.e. separately, thus making it possible to perform two different division operations at the same time via the two symmetrical halves. The division process can thus be performed bidirectionally or on one side (left or right). The operands may be represented in a non-redundant format or in a digit format with a sign, where 'carry-ripple' transfer can be prevented by the representation strategy of the 'non-neighbouring non-zero trits' and a region centred on '1' will be alocated to the absolute value of the mantissa (M) after the standardisation process.