Showing papers on "Electronic packaging published in 1988"

Full panel electronic packaging structure

Abstract: An electronic packaging structure, and a method of making this structure, are disclosed. The electronic packaging structure comprises a full panel, circuitized flexible film semiconductor chip carrier mounted on a circuitized substrate such as a printed circuit board. A plurality of semiconductor chips are mounted on the carrier in a selected pattern, and the carrier, with the chips, is mounted on a matching pattern of bonding sites on the circuitized substrate. Preferably, the circuitized flexible film semiconductor chip carrier is manufactured on a support structure used to facilitate handling of the circuitized flexible film and to facilitate heat transfer from the semiconductor chips mounted on the carrier to a heat sink which is part of the circuitized substrate. Also, the semiconductor chips mounted on the flexible film chip carrier may be tested, and burned in, while on the support structure before the chip carrier, with the chips, is mounted on the circuitized substrate.

A 16mb Dram with an Open Bit-Line Architecture

Abstract: THIS PAPER WILL COVER A 16Mb DRAM with a 6511s RAS access time and 5.4mm x 17.38mm (93.85mm2) chip in a 300mil dual-in-line package. The chip was fabricated in 0 . 5 ~ N-well CMOS technology with double-poly, single-polycide and double-metal. To package a 16Mb DRAM in a 300mil DIP, the memory cell size has t o be less than 4pm2 maintaining a capacitance large enough for alpha-particle-induced soft error tolerance and the stable operation. Open bit-line architecture can provide a small geometry memory cell, resulting in a high density cell array‘. However, in conventional open bit-line architectures, total packing density of 16Mb DRAM cannot be improved, since the scaling of cell size is limited by the layout pitch of the sense amplifiers. To overcome this problem, we developed an open bit-line architecture based on a double layer bit-line and a surrounding Hi-capacitance trench cell s t r n c t ~ r e ’ ’ ~ ’ ~ . Figure 1 shows the circuit configuration of the relaxedsense-amplifier-pitch open bit-line architcture. Memory cells were arranged at all the cross points of word lines and segmented bit lines. The pitch of the sense amplifier is equal to double pitch of the segmented bit lines. The segmented bit lines are connected alternately to either side of the sense amplifiers. The sense amplifiers are connected t o two staggered segmented bit lines of adjacent segments. Further, two sense amplifiers were arranged in between a pair of global bit lines. A word-line selects four memory cells for every pair of global bit lines. In concurrence with the word-line selection, four sense amplifiers on both sides of the selected word-line are activated by SE. The complementary outputs of one of the four sense amplifiers are selectively connected to global bit lines via the segment-select switches controlled by column addresses.

Using Metallic Coatings to Enhance Thermal Contact Conductance of Electronic Packages

Abstract: Recently a new thermomechanical model for coated contacts has been developed and shown to be quite accurate. After a brief overview of the theory, this paper concentrates on illustrating the utility of the new model by applying it to a common electronics packaging problem: heat transfer across an aluminum joint. Several soft metallic coatings are considered, and the thermomechanical model is used to predict the improvement in the contact conductance over that for a bare aluminum-to-aluminum joint. For each coating material, heat transfer performance is presented as a function of the coating thickness, the surface roughness, and the applied pressure. Finally, a parameter is proposed that allows candidate coating materials to be ranked.

High-Density Interconnects For Electronic Packaging

Abstract: High-density interconnect (HDI) is a unique, novel, hybrid approach currently in the development stages at the GE Research and Development Center. Our approach uses polymer layer overlays laminated over bare chips mounted on a substrate. The over-lays are laser-patterned with copper to connect the chips and I/O. The advantages of the HDI hybrid approach can be summarized as follows: •The overlay layer makes the entire chip area available for interconnect lines. •The interconnect has very high density: 2-mil pitch has been demonstrated. •Via and line formation are under computer control. Thus, no patterning mask is used. Chip misalignment is accommodated by computer-adaptive writing. •Copper is the conductor metallization. •The chips can be almost touching. •The interconnect technology accommodates any chip size and mixed chip technologies. •The process is ideal for prototype or moderate volume production. •The overlay can be removed and replaced without chip damage. •Chips are mounted directly on the substrate for good heat dissipation.

Package and packaging method for itemised articles

Abstract: In storage houses operating partially or fully automatically, it is a requirement that the package and packaging accessories take up only a small part of the storage capacity. Plastic bags which are used as packaging accessories and can be filled with air or a gas fulfil this requirement. In the method for packaging, the plastic bag (3) is filled with air or gas (8) from the outside by means of an air or gas supply device and is closed. After the filling operation, the plastic bag (3) is a shock-absorbing padding or compensating element, which spreads out in the free space of the packaging container (1), between the itemised articles (2) and the package wall of the packaging container (1). The package and the packaging method are suitable for packaging itemised articles, in particular small items.

Trends in semiconductor packaging, a merchant house view

Abstract: Semiconductor packaging is being driven in two major directions by the demand for increased system operating speeds and higher functional density. Most prominent is the trend toward higher functional integration on the die, resulting in both a larger die size and decreased feature size. The other major trend is the mechanical integration of multiple devices in a single package. These trends require improved package-design methods that include electrical and thermomechanical modeling, improved data on material properties that drive package reliability, and novel methods of reliability testing to meet the very low defect levels that will be required in next-generation electronic equipment. >

Electronic packaging: a systems approach to radiation curing

Abstract: UV-curable conformal coatings are described which retain the quality performance properties of RTV and heat-cured materials while being capable of curing in seconds at lower heat levels. The significant advantage of these materials is that they are free of solvents. The coatings and the equipment to process them were developed simultaneously. This work demonstrates the benefits of this interactive approach to materials and equipment development. >

Method of packaging goods

Abstract: of EP03067402.1 In partially or fully automatically operating goods stores, it is a requirement that packaging and packaging aids take up only a small part of the storage capacity. Plastic bags, which serve as packaging aids and can be filled with air or a gas, fulfil this requirement. 2.2 In the packaging method, the plastic bag (3) is filled with air or gas (8) from the outside via an air or gas feed device and is closed. After the filling operation, the plastic bag (3) is present as a shock-absorbing packing and compensation element, extending in the free space of the packaging container (1), between items (2) of a unit load and the packaging wall of the packaging container (1). 2.3 The packaging and the packaging method are suitable for the packaging of items of a unit load, in particular small items.