Showing papers on "Fault coverage published in 1970"

Sequential Machines Capable of Fault Diagnosis

Abstract: By a checking sequence for a sequential machine, we mean an input-output sequence with a special property such that, when the input sequence is applied to the machine, the decision whether or not the machine operates correctly can be made by comparing the output sequence with the output of the machine.

Generation Of Fault Trees From SimulatedIncipient Fault Case Data

Abstract: Fault tree analysis is widely used in industry in fault diagnosis. The diagnosis of incipient or 'soft' faults is considerably more difficult than of 'hard' faults, which is the situation considered normally. A detailed fault tree model reflecting signal variations over wide range is required for diagnosing such soft faults. This paper describes the investigation of a machine learning method for the automatic generation of fault trees for incipient faults. Features based on the FFT (Fast Fourier Transform) of the time response simulations are used are used to provide a training set of examples comprising records of fault types, severity and feature list. The algorithm presented, called IFT, is derived from the ID3 algorithm for the induction of decision trees. A significant aspect of this approach is that it does not require any detailed knowledge or analysis of the application system. All that is needed is a 'black-box' model of the system; i.e. knowledge of what faults arise from measurable quantities taking on particular values. The proposed procedure is illustrated using detailed simulation results for a servomechanism typically found in machine tool applications and the results to date indicate the feasibility of the approach.

A method of test generation for fault location in combinational logic

Abstract: The Path Generating Method is a simple procedure to obtain, from a directed graph, an irredundant set of paths that is sufficient to detect and isolate all distinguishable failures It was developed as a tool for diagnostic generation at the system level, eg, to test data paths and register loading and to test a sequence of transfer instructions But it has been found to be a powerful tool for test generation for combinational logic networks as well

Design of Automatic Detection Model for Single-phase Earth Fault in Distribution Network

Abstract: The current distribution network single-phase ground fault detection model knowledge expression is poor, its production process only based on the normal distribution network sample data, no single-phase ground fault data, did not make full use of a prior knowledge, resulting in low detection accuracy. The automatic detection model of single-phase earth fault of new distribution network is proposed. The fault characteristic vector is taken as the input vector, and the degree of matching between the input vector and the weight vector element is introduced as the second layer. The fault vector is used as the input vector, and the fault vector is used as the input vector. Node input, the second layer of the output as the third layer of the input, the model training, the output of the results of the distribution network is a single-phase ground fault detection results. The experimental results show that the proposed model has high detection accuracy.Â

Transitional Delay Fault Test Generation Using AGenetic Algorithm

Abstract: With the continuous technological advancements in digital electronic circuit technology devices are becoming even more complex, it is essential that a high level of operational reliability is maintained which is why there is always a requirement for new and improved test methodologies. A fault condition in a digital circuit may be the result of a manufacturing problem causing physical imperfection in the device, this imperfection may be open circuit or short circuit connections, or a flaw that changes other characteristics of the device. The propagation of a gate may be affected introducing a delay defect into the circuit, often creating timing problems, which have always proved difficult to detect. This paper presents a new approach to the generation of test patterns that detect gross delay defects in combinational VLSI circuits. In O'Dare and Arslan [1] the authors presented a technique that implemented a genetic algorithm (GA) for the generation of test patterns to detect single stuck-at-faults in combinational VLSI circuits. In order to generate a test for delay faults it is necessary to create a transition in logical state at the fault site within the circuit, the only way to achieve this is by generating pairs of test patterns . The first test pattern initialises the state of all nodes within the circuit, the second test pattern is then used to force the required transition at the designated test node. The problem of test generation for delay faults is considerably more complex than that of test pattern generation for single stuck-at-faults presented in O'Dare and Arslan [1], with an increase in search space size from 2 n to 2 2n for an n input circuit. The problem is further augmented by the necessity of applying the two test patterns in a strict ordered sequence to create the required transition. The authors have therefore developed a new genetic test technique to overcome the problem, using chromosomes-pairs to represent the test patterns. The GAs primary component is a dynamically evolving Global Record Table (GRT), which is used to guide the search towards optimal test pairs in an otherwise complex solution space, producing a compact and efficient set of test pattern-pairs as the GA evolves. The experimental results presented in this paper are compared with other research results for well known combinational benchmark circuits.