Showing papers on "Fault coverage published in 1972"

Path Sensitization, Partial Boolean Difference, and Automated Fault Diagnosis

Abstract: A tool employed in automated fault diagnosis is emphasized: path sensitization by partial Boolean difference analysis. Motivated by the analogy between a test system and a communication system, a model for fault detection of a logic net is outlined from the standpoint of information theory. The classical ``path sensitizing'' technique is made systematic using the partial Boolean difference. This technique is based on a new theorem on the partial Boolean difference. Finally, a programmable fault detection algorithm is presented along with an example.

Fault detection and isolation in a data processing system

Abstract: A fault interrupt system is arranged, upon the detection of a fault to cause a processor in which the fault is detected to enter a fault check-out routine. Successive fault conditions detected while performing the fault check-out routine causes re-entry into that routine. A faulty processor is therefore, trapped within the fault check-out routine. Additionally the detection of a fault causes the master capability register of the fault detecting processor to be overwritten with a capability defining a special capability table which is only relevant to the fault check-out programs. By this mechanism the faulty processor cannot, even under fault conditions, gain access to any storage areas outside those of the fault check-out programs. In the multi-processor/multi-storage module system of the PP250 a number of copies of the fault check-out programs and related workspace areas on a one copy per store module basis are provided together with a special capability pointer for each processor of the system and each entry into the check-out program is performed using a different store and therefore entry mechanism into the check-out programs copy so that intermittent processor faults or particular storage module faults will not maintain the processor indefinitely in the check-out program.

Generation of Fault Tests for Linear Logic Networks

Abstract: In this note we study the problem of fault detection in linear logic networks. We introduce the concept of error vectors that indicate how the effect of a fault propagates through a network. These vectors allow one to identify redundancies in the network as well as calculate the output of the network given a fault and an input. Problems related to fault diagnosis and the detection of multiple faults are also considered.

Fault simulation system for determining the testability of a non-linear integrated circuit by an electrical signal test pattern

Abstract: A system involving the use of fault simulation for determining whether a proposed non-linear integrated circuit is testable by a proposed incremental bilevel electrical signal test pattern. The system, which is particularly advantageous in determining the testability of integrated circuits having sequential logic, involves the conversion of the bilevel electrical test pattern into a corresponding three-level test pattern, and the application of said three-level pattern to a three-level "good" circuit simulation of the integrated circuit and to a number of three-level "bad" circuit simulations of said circuit, each of said "bad" circuit simulations being representative of a different stuck fault condition which is to be determined by the test pattern.

An Improved Bound on the Length of Checking Experiments for Sequential Machines with Counter Cycles

Abstract: The bound on the length of checking experiments derived by Murakami et al. [1] is improved by using a more efficient output specification in the counter cycle.

Improved Procedures for Determining Diagnostic Resolution

Abstract: The definition of the generalized fault table [1] is expanded to cover a representation employing more than one fault q cube per fault pattern. On the basis of this expanded definition and simple concepts from a cover algebra, a new procedure is developed for finding first- and second-order diagnostic resolutions.

Secondary techniques for increasing fault coverage of fault detection test sequences for asynchronous sequential networks

Abstract: The generation of fault detection sequences for asynchronous sequential networks is considered here. Several techniques exist for the generation of fault detection sequences on combinational and clocked sequential networks. Although these techniques provide closed solutions for combinational and clocked networks, they meet with much less success when used as strategies on asynchronous networks. It is presently assumed that the general asynchronous problem defies closed solution. For this reason, a secondary procedure is presented here to facilitate increased fault coverage by a given fault detection test sequence. This procedure is successful on all types of logic networks but is, perhaps, most useful in the asynchronous case since this is the problem on which other techniques fail. The secondary procedure has been designed to improve the fault coverage accomplished by any fault detection sequence regardless of the origin of the sequence. The increased coverage is accomplished by a minimum amount of additional internal hardware and/or a minimum of additional package outputs. The procedure presented here will function as part of an overall digital fault detection system, which will be composed of: 1) a compatible digital logic simulator, 2) a set of fault detection sequence generators, 3) secondary procedures for increasing fault coverage, 4) procedures to allow for diagnosis to a variable level. This research is directed at presenting a complete solution to the problems involved with developing secondary procedures for increasing the fault coverage of fault detection sequences. iii

Procedures for increasing fault coverage for digital networks

Abstract: The following definition for a fault detection test (fdt) will be used throughout this paper: an input sequence x (of length one or more) for a given network m is a fault detection test for fault fi, located in m, if the output response to x for m with no faults present and the output response to x for m with fi present, differ.