Showing papers on "Fault detection and isolation published in 1975"

Probabilistic Treatment of General Combinational Networks

Abstract: In this correspondence two methods are given for calculating the probability that the output of a general combinational network is 1 given the probabilities for each input being 1. We define the notions of the probability of a signal and signal independence. Then several proofs are given to show the relationship between Boolean operations and algebraic operations upon probabilities. As a result of these, two simple algorithms are presented for calculating output probabilities. An example of the usefulness of these results is given with respect to the generation of tests for the purpose of fault detection.

Polynomially Complete Fault Detection Problems

Abstract: We look at several variations of the single fault detection problem for combinational logic circuits and show that deciding whether single faults are detectable by input-output (I/O) experiments is polynomially complete, i.e., there is a polynomial time algorithm to decide if these single faults are detectable if and only if there is a polynomial time algorithm for problems such as the traveling salesman problem, knapsack problem, etc.

An Advanced Fault Isolation System for Digital Logic

Abstract: Advances in integrated circuit technology are decreasing acquisition cost per function of digital hardware while system software costs are increasing. The hardware advances allow practical implementation of more sophisticated and complex systems which have fewer components, but which may present severe test and maintenance problems due to their complexity. As a result, the use of built-in test (BIT) hardware in place of software becomes increasingly attractive. The Navy funded Advanced Avionics Fault Isolation System (AAFIS) concept utilizes BIT logic for cost-effective fault detection and fault isolation to a digital subsystem and to the faulty module therein. Added logic, available at low cost with advanced microelectronics, is used to perform test pattern generation in each subsystem and to code over the test sequence the outputs and test points on each subsystem module. The coded test response is compared to a predetermined constant. The OR of resulting module pass-fail signals indicates subsystem faults, while identification of a module fail signal provides isolation to a faulty module. Practical coding techniques are presented, with tradeoff of speed, test effectiveness and logic requirements for each. BIT logic design and simulation results verify high fault detection and moderate added logic for BIT.

The application of nonlinear filtering to fault detection in linear systems

Abstract: Using nonlinear filtering theory, the equations satisfied by the optimal state estimator and fault detector for a linear system are derived. These suggest an implementable scheme based on reparametrization of the Kalman filter.

Fault Masking in Combinational Logic Circuits

Abstract: An important problem in fault detection is to verify whether a single-fault test set is able to detect all multiple-faults. This paper provides a solution to the above problem. It is known that a test set derived for the detection of some fault may fail this purpose in the presence of an additional fault. This phenomenon is called masking among faults, and is of great importance in the derivation of a test set which detects all multiple-faults. This paper investigates the masking relations among faults in a combinational logic circuit. For this purpose a transform for the circuit is defined and a model for fault analysis is constructed. This transform and model reduce the number of faults which have to be considered in order to achieve the detection of all multiple-faults. An algebraic procedure yields the derivation of the masking relations. A problem which arises, namely the existence of a set of faults forming a loop of masking relations is considered. An application is presented: starting with a test set derived under the single-fault assumption it is shown how to extend this test set so that it detects all multiple-faults. All of the results in this paper are valid for general multiple-output circuits. For simplicity in the exposition, the single-output case is examined.

An Algorithm for the Generation of Test Sets for Combinational Logic Networks

Abstract: An algorithm is developed for generating a single-fault detection test set to be used in a combinational logic network. This algorithm has two unique characteristics. 1) When a test is generated, a list of faults detected by this test is available. Fault simulation, therefore, is not required after the test has been generated. 2) It generates a test set rather than a single test. Each test, with the exception of the first one, is based on a previous test. Repetition of effort and overlapped coverage of faults for different test generations are thus reduced.

Concurrent software fault detection

Abstract: A graph theoretic model for software systems is presented which permits a system to be characterized by its set of allowable execution sequences. It is shown how a system can be structured so that every execution sequence affected by a control fault is obviously in error, i.e., not in the allowable set defined by the system model. Faults are detected by monitoring the execution sequence of every transaction processed by the system and comparing its execution sequence to the set of allowable sequences. Algorithms are presented both for structuring a system so that all faults can be detected and for fault detection concurrent with system operation. Simulation results are presented which support the theoretical development of this paper.

Properties of Faults and Criticalities of Values under Tests for Combinational Networks

Abstract: This correspondence discusses the properties of faults in combinational networks and their relationships with fault-detection and fault-location test sets.

Low impedance fault detection system and method

Abstract: Isolation of a wired-OR fault on a printed circuit board is accomplished by first powering up the circuit board, then injecting a short pulse on the common buss and detecting the current flow by use of a ferrite core. The ferrite core is sufficiently small that it can be moved about the circuit board to the terminals of the various components that are connected to the current buss in a wired-OR configuration. The change of inductance created by the magnetic field associated current pulse flowing through the terminal of a component sinking the current creates a ringing effect which is amplified and compared against a reference voltage. The output of the comparator circuit is used to create a fault alarm signal.

Multiple Fault Detection for Combinational Logic Circuits

Abstract: An algorithm for generating test sets to detect all the multiple stuck-at-faults in combinational logic circuits is presented. This algorithm generates a test set using a set of functions, called representative functions, which consists of much fewer functions than all possible multiple stuck-at fault functions, but is sufficient for test generation. Two different methods of finding such a set of representative functions are presented. The test sets derived from the set of representative functions obtained by the first method will be smaller than that by the second method, but the second method is much simpler than the first especially for highly redundant circuits. Nevertheless, the complexity of this algorithm using the first method is about the same as that of Bossen and Hong's algorithm which is the simplest existing algorithm under the multiple stuck-at fault assumption, and yet the number of tests in a test set generated will always be smaller for redundant circuits and the same for irredundant circuits as that generated by Bossen and Hong's algorithm for irredundant circuits.

Ground Fault Protection for Electric Utility Generating Station Medium Voltage Auxiliary Power Systems

Abstract: Many generating station 480-volt auxiliary power systems employ a WYE distribution system with the source neutral solidly grounded. Because of the arcing nature of some ground faults, the ground fault currents developed on these systems are often too low to operate phase overcurrent protective devices. As WYE systems became more popular, a more sophisticated approach to protection was needed, resulting in the development of many new protective devices for ground fault protection. This paper reviews the application of such ground fault protective devices for use in 480-volt auxiliary power systems of generating stations. In addition, some modifications to existing products are suggested.

Modeling transient faults in TMR computer systems

Abstract: In this paper we report the development of a technique for modeling transient faults in redundant computer systems. Transient faults are characterized by their arrival rate and their duration. Fault detection, transient recovery, and the effect of permanent faults are included. A fault occurrence/recovery status state diagram is drawn to illustrate the operational status of the system while undergoing faults. The state diagram is used to formulate the equations for the mission failure probability. The techniques are then applied to a triple modular redundant computer system.

Low power solid state three-phase overcurrent/undercurrent protection circuit

Abstract: A three-phase current sensing fault detection network has been developed employing an all solid state design. Systems equipped with such a network will be deprived of three-phase power in the event that either excessive or insufficient current is monitored in any or all of the three-phase power lines. The system design can be expanded to include a system shutdown capability for any number of sensing inputs from various critical portions of the circuit being monitored.

Design of totally self-checking asynchronous sequential machines

Abstract: : Properties of state assignments and circuit realizations that lead to totally self-checking asynchronous machine designs are studied. The state variables and the outputs are encoded so that all single and unidirectional faults cause the machine to assume a noncode state or output. Several state assignment methods are presented. One is the two-rail assignment where the feedback lines are checked with a two-rail checker tree. It is shown that any two-rail checker cannot be used because the state assignment does not in general have all the two-rail codewords. Therefore a checker tree that can be checked by the state assignment code must be selected. An algorithm for finding such a tree is presented. The effect of a fault on the encoded outputs is studied. A self-checking circuit produces a noncode output for at least one code space input. It is shown that a self-checking asynchronous machine will produce a noncode output for at least one input sequence which occurs under normal operation. For this design, the destination sets of each input column of the flow table are encoded with a constant weight or another unordered code. Redundancies in the code and in the realization are discussed. It is shown that extra outputs can be used for the detection of primary input faults and for a class of flow tables for faster fault detection.

Failure Isolation for a Minimally Redundant Inertial Sensor System

Abstract: The application of two-degree-of-freedom inertial sensors in a minimally redundant strapdown configuration is considered. The potential improvement in reliability which can be achieved by exploiting the failure isolation capability unique to this configuration is evaluated. A unified, statistical approach to the detection and isolation of both hard and soft sensor failures is presented. The effectiveness of this unified approach to FDI in terms of the mean time to detection, the mean time between false alarms, and the accumulated attitude error prior to detection is indicated by simulation results.

Alarm system for a skid control system

Abstract: In a skid control system for fluid actuated brakes of a wheeled vehicle, it is necessary to provide a fault detection unit for detecting a dangerous fault condition of the skid control system and disconnecting the skid control system from an electric source. There is also provided another fault detection unit for detecting a light fault condition of the skid control system and a fault condition of a power circuit during travel of the vehicle, and indicating the fault condition without disconnecting the skid control system from the electric source. The initial condition of the skid control system immediately after power throw is checked and the indication is carried out when the skid control system is in a normal condition, and the indication is eliminated when the velocity of the vehicle exceeds a predetermined value.

A statistical method for test sequence evaluation

Abstract: A method for test sequence evaluation based on random sampling of detectable faults is presented. This method can be incorporated into most logic simulation codes which use the parallel machine method of fault detection.

Fault detection indication system

Abstract: A fault detection and indication system for electrically energized apparatus. The system connects to a number of sensors which actuate series switches in a power supply control circuit for the apparatus. If any switch contacts open, the control circuit deenergizes the apparatus. The fault detection and indication system connects to these switches and displays the status of the switches by means of first and second indicator lights.

Two-frequency instrument landing system with integral monitor

Abstract: A two-frequency capture-effect instrument landing system employs a single localizer antenna array for both course-frequency and clearance-frequency radiation. The composite course and clearance signals are formed by networks that utilize trees of hybrid power dividers to effect unequal power division and distribute the signals to the antenna feeders. Integral monitoring is provided by similar networks, operating backwards in a functional sense, which recombine samples of the RF energy on the antenna elements and separate the same into the basic, frequency-separated course and clearance signal components. Redundant monitoring for antenna fault detection is provided by detecting RF signal levels on unused ports of the monitor circuit power dividers.

AnAdvanced Fault Isolation System forDigital Logic

Abstract: Advances inintegrated circuit technology aredecreas- ingacquisition costperfunction ofdigital hardware whilesystem software costs areincreasing. Thehardware advances allow practical implementation ofmoresophisticated andcomplex systems which havefewer components, butwhich maypresent severe test andmain- tenance problems duetotheir complexity. Asaresult, theuseof built-in test(BIT) hardware inplace ofsoftware becomes increas- ingly attractive. TheNavyfunded Advanced Avionics Fault Isolation System(AAFIS) concept utilizes BITlogic forcost-effective fault detection andfault isolation toadigital subsystem andtothefaulty moduletherein. Addedlogic, available atlowcostwithadvanced microelectronics, isusedtoperform testpattern generation ineach subsystem andtocodeoverthetestsequence theoutputs andtest points oneachsubsystem module. Thecodedtest response iscom- pared toapredetermined constant. TheORofresulting module pass- fail signals indicates subsystem faults, while identification ofamod- ulefail signal provides isolation toafaulty module. Practical coding techniques arepresented, withtradeoff ofspeed, test effectiveness andlogic requirements foreach. BITlogic design andsimulation results verify highfault detection andmoderate addedlogic forBIT. IndexTerms-Automatic testequipment (ATE),built-in test (BIT), fault isolation, large-scale integration (LSI) testing, self test, subsystem test, system maintenance, test response.

Fault detection relay

Abstract: PURPOSE: A relay is used for a fault detecting element in a power system for detect detecting the combination of current and voltage or the product of the voltage, it can effect a high speed operation of digital quantity, and is easily operated repidly and accurately by extending the operation range. COPYRIGHT: (C)1977,JPO&Japio

Alarm system for indicating a fault condition of an anti-skid braking control system

Abstract: In an alarm system wherein a fault detection unit and a fault indication unit are spaced away from each other, long wires for detection signal transmission and for power supply, etc., are necessary. A fault indication driving circuit is provided within or adjacent to the fault indication unit, the bias voltage of the fault indication driving circuit being determined with the use of the detection signal transmission wire and the power supply wire in such a manner that the fault indication is enabled when one of the long wires is accidentally broken or placed in poor connection condition.

Digital data system: Testing and maintenance

Abstract: Reliability and maintainability are important aspects of the service objectives for the Digital Data System. Consequently, maintenance planning was an essential element in the DDS development. Maintenance features provided by the system include in-service performance monitoring, protection switching, comprehensive alarms, and the means for rapid fault isolation and repair.

Application of likelihood ratio methods to failure detection and identification in the NASA F-8 DFBW aircraft

Abstract: A system for on-line detection and identification of aircraft sensor and effector failures is developed. The heart of the system is a state estimator which provides accurate, real time estimates of the aircraft states. These estimates are used both to provide failure analysis and as inputs to the flight control system. Because the sensors measure functions of the aircraft state, the state estimator also provides running estimates of what it believes each sensor output ought to be, based upon the previous history of sensor outputs and commanded control inputs. Because of the relatively large number of sensors, of various types, that are available; there is an abundance of observability. Thus, failure of a single sensor will not greatly degrade the state estimates and in the event of a sensor failure the output of the failed sensor will diverge from the estimated value. The divergence is monitored and decision logic, based upon likelihood ratio tests, is employed for sensor failure detection and identification (FDI). The likelihood ratio methods provide a systematic, quantitative means for design of the decision logic. This FDI technique is in direct contrast to techniques which employ voting among like sensors and therefore require three sensors of every type in order to identify the single failure of any one of them. The present technique, employing likelihood ratio methods, requires fewer sensors because of its utilization of the redundant information available from sensors of different types which are coupled through the dynamics of the aircraft.

Instructional Strategies Using Low-Cost Simulation for Electronic Maintenance

Abstract: : A variety of instructional strategies employing visual aids were developed to improve electronic maintenance training on a complex system (Improved Hawk) Large color photos of control/indicator panels, supplemented by color slides, were developed for use in the classroom Supplementary exercises were developed for students to use while awaiting their turn on the equipment Students receiving the experimental training demonstrated significantly greater facility in checks, adjustments, and fault isolation than did the control group

Fault Diagnosis in Combinational Tree Networks

Abstract: In this paper, which is a follow up to [8], we are concerned with the problem of generating minimal experiments to locate and diagnose faults in combinational tree networks. We establish lower bounds on the necessary number of fault-locating tests and show how, in a systematic way, such experiments can be obtained. Two types of testing procedures are considered—adaptive and preset.

Fail-Safe Asynchronous Sequential Machines

Abstract: Fail-safe circuits are designed to assume a 1 (1-fail-safe) or a 0 (0-fail-safe) output state upon failure. This correspondence extends fault detection techniques previously presented [1] to include the design of fail-safe asynchronous sequential circuits. Faults causing failures in the internal state logic and the output state logic circuitry are treated. These failures are assumed to be symmetric and the resulting circuit realizations require less hardware than realizations derived from previously presented techniques.

Theory of Fault Tolerance.

Abstract: : The first phase of a long range program to develop a theoretical base for the design and evaluation of fault tolerant digital systems is summarized. The purpose of this effort was to investigate the feasibility of representing fault tolerant phenomena with two existing Labeled Graph models, LOGOS and Petri Nets. LOGOS and Petri Net models were used to represent systems at a functional level. Functional faults were hypothesized to describe the effect of a fault mechanism from a functional viewpoint. Functional faults were found to provide high leverage over traditional 'Stuck-At-One' or 'Stuck-At-Zero' analysis. Models were developed which describe: (1) The non-faulty system function; (2) The faulty system operation; (3) Fault detection techniques; and (4) Fault recovery schemes. The results of modeling several candidate fault tolerant system problems reaffirmed our belief in the utility of Labeled Graphs as a representation language for fault tolerant phenomena. We found both models concisely described the structure and dynamics of a control system and provided insight into the effect of fault detection and recovery mechanisms on a given fault mechanism.

Fault-Detection Experiments for Parallel-Decomposable Sequential Machines

Abstract: Methods are presented for designing fault-detection experiments for sequential machines which are realized as parallel connections of simpler component machines. The outputs of these components are assumed to be inaccessible for measurement but it is shown that knowledge of the structure can be utilized to design simpler experiments. The procedure is based upon placing all components but one in a fixed reference state prior to measuring input/output sequences for this one component in order to deduce its state table. This means that the only measurable transitions are those which return the other components to their reference states. Such transitions are made in response to application of restricted input sequences and it is necessary that the state table be deduced from such a set of observations.

Safeguard data-processing system: Maintenance and diagnostic subsystem

Abstract: The Safeguard Maintenance and Diagnostic Subsystem (M & DSS) is a unique, independent, hardware group within the data-processing system through which the nonreal-time functions of fault detection and isolation are performed. In this paper, the M & DSS hardware and fault detection software are described and system performance is reviewed.