Showing papers on "Fault detection and isolation published in 1981"

Fault detection and diagnostic system for automotive battery charging systems.

Abstract: An in situ self-diagnostic automotive alternator battery charging system is disclosed. Included are: a battery; voltage regulator sensing battery voltage and generating an excitation signal; and an alternator driven by a vehicle engine provide a rectified electrical signal to charge the battery in response to the excitation signal. Electronic circuit status detectors, variously coupled to the battery, voltage regulator and alternator, maintain a first logic state when a corresponding signal characteristic is within a predetermined range and a second logic state when the corresponding characteristic is outside the predetermined range. Combinatorial logic means respond to a logic state sequence from the detectors to identify predetermined sequences of the logic states resulting in the identification of faults in the charging system. The logic means also provides a warning to the operator of detection of a fault and a display of the location of the fault as occurring in one of the major components of the charging system.

Probabilistic Assessment of Transient Stability in a Practical Multimachine System

Abstract: The application of probabilistic techniques in the quantitative evaluation of power system reliability is steadily increasing. Probability methods are being used extensively in the assessment of static adequacy. Their application to the evaluation of transient or dynamic phenomena has not yet, however, been widely utilized. The probabilistic nature of the transient stability problem and the inclusion of the probabilities associated with the initiating factors such as the type, location and clearance of faults in the analysis of a simple single machine-infinite bus system has been demonstrated in a recent paper.1 The present paper addresses the problem of transient stability analysis in a practical multimachine system from a probabilistic view-point. The basic concepts developed in Reference ! are applied to a simplified 33 bus model based on the Saskatchewan Power Corporation (SPC) system, to demonstrate the technique of considering the probabilities associated with the occurrence and clearance of faults. Transient stability indices for each line, for different types of faults and a single stability index for any fault are obtained. A single stability index for the overall system is evaluated for different fault types and amy fault using actual system outage statistics. The effect of fault clearing and reclosing times on the system stability is investigated for the most critical line in the system.

A Fundamental Concept for High Speed Relaying

Abstract: This paper describes a fundamental approach for detecting the direction to a power system fault within the first milliseconds following the fault inception. The method is based on a combined evaluation of the voltage and current deviations generated by the fault occurrence. Design considerations and test results based on numerical simulations and on a transient network analyser are presented. The method solves several problems occurring in conventional relaying and is suitable for use in ultra high speed protection systems which employ a fast telecommunication channel between the ends of the protected network

Automatic Test Generation for Stuck-Open Faults in CMOS VLSI

Abstract: Because of its relative low power dissipation, intermediate speed, and high density, CMOS (Complementary Metal Oxide Semiconductor) will emerge as one of the leading VLSI technologies. Therefore, testing CMOS VLSI circuits is very important. The conventional stuck-at fault assumptions are not sufficient for modeling some faults that are peculiar to CMOS circuitry, specifically the stuck-open faults. These faults are sequential in nature. This means that when a fault occurs in a combinational circuits, the circuit behaves as a sequential circuit. Therefore, special test pattern generation techniques are necessary to test this type of faults. In this paper, we present an algorithm which uses the conventional stuck-at list to detect some stuck-open faults. Some modifications of the conventional testing procedure are necessary. Such modifications and their associated programming effort are expected to be straight forward. For the stuck-open faults that cannot be detected by the conventional stuck-at test list, a second algorithm is described that generates the tests for such faults. The algorithm generates the test if such a test exists. If not, the fault is declared as undetectable. First, we will discuss the stuck-open fault and its peculiarity to CMOS circuitry. Second, we will describe the step-by-step algorithms used to generate a complete test list for this type of fault. Finally, a small example circuit will be used to illustrate the new test generation technique and some conclusive remarks will be given.

A fault detection and isolation methodology

Abstract: A fault detection and isolation methodology has been developed for validation of sensors and plant components. Significantly, the isolation of most consistent and inconsistent subsets of measurements for the purposes of estimation and failure detection is performed on the basis of a multi-level, as opposed to the usual bi-level, fail/no fail, characterization of the inconsistencies among measurements. This is achieved by the concurrent checking of the relative consistency of smaller size subsets of measurements. The algorithm has been computer-coded for real time applications, and validated by on-line demonstration in an operating nuclear reactor.

Electric command spoiler system

Abstract: An aircraft spoiler control system wherein each of a plurality of spoilers is driven by an electrically responsive actuator. Sense signals representative of the aircraft's control wheel rotation, speedbrake lever deflection, flap position and air/ground status are processed by logic which produces a corresponding control signal for each actuator. Fault detection circuitry switches in a back-up actuator control signal if a fault occurs in the active control circuit.

Fault detection system as for locating faulty connections in a cable television system

Abstract: A fault detection system is provided for detecting and locating faulty connections in a cable TV system. First and second signals are generated at the head end transmitter. The first signal is a continuous wave signal. The second signal is a pulse modulated sine wave signal. A fault is indicated by the reception of a beat frequency signal between the first and second signals generated at the location of the faulty connection and returned to the head end. The location of the fault is determined by measuring the time interval between the transmission of the first and second signal and the return of the beat frequency signal, and relating such time interval measurement to the corresponding distance between the head end and the faulty connection.

LSI Product Quality and Fault Coverage

Abstract: At present, the relationship between fault coverage of LSI circuit tests and the tested product quality is not satisfactorily understood. Reported work on integrated circuits predicts, for an acceptable field reject rate, a fault coverage that is too high (99 percent or higher). This fault coverage is difficult to achieve for LSI circuits. This paper proposes a model of fault distribution for a chip. The number of faults on a defective chip is assumed to have a Poisson density for which the average value is determined through experiment on actual chips. The procedure, which relates the model to the chip being studied, is simple; one or more fabricated chip lots must be tested by a few preliminary test patterns. Once the model is characterized, the required value of fault coverage can be easily determined for any given field reject rate. The main advantage of such a model is that it adapts itself to the various characteristics of the chip (technology, feature size, manufacturing environment, etc.) and the fault model (e.g., stuck-type faults). As an example, the technique was applied to an LSI circuit; realistic results were obtained.

Method and apparatus for fault detection

Abstract: This invention relates to methods and apparatus for detecting the occurrence of a fault on a conductor or transmission line and for protecting the conductor or line in accordance with the determination of fault. The instantaneous value of the voltage (V) and current (i), or the modal components of that voltage and current in the case of a polyphase line, are formed into two functions S lR and S 2R , which are of the general form V-iR and V+iR respectively where R is a replica of the surge impedance of the line. Superimposed components of these functions are derived by continuously subtracting the steady-state value of each function from its instantaneous value. The sequence in which the functions obtain a value outside a predetermined band of values is monitored to provide an indication of the existence and direction of a fault with respect to the measuring point. Trip and block signals are generated for operating circuit breakers.

Method of preventing erroneous gear selection in a vehicle transmission

Abstract: The invention relates to a method for preventing at a vehicle gearbox selection of an operationally erroneous gear in the absence of a gear change regulating speed signal. The absence of the gear change regulating signal is detected by a fault detection circuit or by a fault detection routine, which thereby sends an output signal to an operative circuit or the like. The operative circuit ensures that erroneous gear selection is prevented and/or triggers a fault indication. With the intention of ensuring that a fault already existing when the vehicle starts can be detected, the invention is essentially distinguished in that during the fault detection routine it is determined whether the engine is running, whether a forward gear is engaged, the clutch is engaged, and whether and with these conditions extant whether the speed has attained a given minimum speed within a predetermined time. If said minimum speed is not attained, an output signal is sent to the operative circuit which presents an erroneous gear selection and/or triggers a fault indication.

Interconnect fault detector for LSI logic chips

Abstract: A large-scale integrated circuit (LSI) chip has an individual voltage level sensing circuit connected with each input and output connecting pin so that isolation between the pins is maintained and so that the individual level sensor output can provide an indication of an abnormal voltage on the input/output pin. The outputs of all level sensors for all input and output pins is connected in common to the input of a comparator circuit. The comparator circuit has a fault detection threshold voltage input and provides a fault indication output signal whenever the voltage input from the level sensor circuits is outside of the detection threshold voltage range. A number of logic chips will have particular input/output pins connected together in a circuit in conventional applications. An open circuit anywhere in the interconnected network will cause some number of input/output pins dependent on the fault location to be pulled out of the detection threshold voltage range. Similarly, any short circuit to ground condition will also cause a voltage shift outside of the detection threshold voltage range. Further, interconnect faults which result in impedance mismatch and cause a "ringing" signal voltage outside of the threshold detection voltage range, will also be detected as a fault signal. Thus, the fault detection system of the present disclosure will detect a number of types of faults in interconnection networks of various logic chips.

Random testing of integrated circuits

Abstract: The paper concerns fault detection by applying a random input sequence simultaneously to a circuit under test and to a reference circuit. The objective is to determine the length of the input sequence to be applied, to obtain a given detection quality (detection probability). The paper gives a summary of the results which have been obtained for combined circuits, memories, SSI, and MSI sequential circuits.

Electromechanical device drive circuit fault detection apparatus

Abstract: Apparatus is disclosed for verifying the proper operation of a drive circuit (43) which controls the application of power to an electromechanical device, e.g., a manually reset circuit breaker (36). The apparatus includes means (60) for applying a control signal to the drive circuit to cause it to briefly apply power to the electromechanical device, where the interval of time over which power is applied is too brief to cause actuation of the device. Means (64) are also provided for sensing the power applied to the device to verify that the drive circuit has properly responded to the control signal.

Multiple fault testing of large circuits by single fault test sets

Abstract: A general theory is presented in this paper to quantitatively predict the multiple fault coverage capability of single fault detection test sets in combinational circuits. The theory is unique in that it provides greatest lower bounds on the coverage capability of all possible circuits of concern by a simple table-look-up process. All the results known so far in this area are seen to be special cases of the theory. The more important contribution of the theory, however, is seen in its predictions made for reconvergent internal fan-out circuits. Most unexpectedly, the multiple fault coverage of such circuits by single fault test sets is discovered to be extremely precarious. Such results clearly have alarming implications in LSI and VLSI testing.

Recovery from Temporary H.V.D.C. Line Faults

Abstract: Modelling techniques are described to simulate the behaviour of a.c./d.c. systems following temporary d. c. line short-circuits. The basic tools employed are a small step dynamic simulation and a multimachine transient stability programme. Test results are shown to illustrate the speed of recovery from a d.c. short-circuit. The effects of fast fault detection, fault development and line re-energization controls are also discussed.

Photoelectric measuring ruler including fault detection apparatus

Abstract: A measuring rule has a coilable steel measuring blade extensible through an opening in a housing and is marked along its length with regularly spaced dark areas separated by light areas. Two pairs of light sensors are located near the rule each associated with a light emitter. Each sensor is 180° out of phase with the other sensor of the pair and 90° out of phase with the other two sensors. The outputs of each pair of sensors are used to produce a difference signal. The difference signals are used by a counter to measure the magnitude and direction of movement of the blade. Each sensor output signal is divided by voltage divider to give a divided signal and each sensor output signal is compared with the complementary divided signal at the instant the difference signal of the other pair of sensors changes state and a fault signal is generated if its minimum is larger than the maximum of the complementary divided signal. The fault signal is generated when an abnormal deviation in a sensor output signal occurs even if the deviation is insufficient to cause a count error.

Automatic fault detection system for a machine tool

Abstract: An automatic fault detection system for use with machine tools to detect the breakage or absence of the tool, the presence and/or absence of a portion of the workpiece, and to prevent the normal cycle of operation of the machine when such condition exists, includes a sensor having a rod, a power port and a pair of pressure sensing ports. First and second pressure sensing switches are connected to the sensing ports wherein the failure of the sensor rod to fully retract or to advance before or beyond good check stroke position respectively exhausts the pressure sensing switches preventing operation of the machine cycle.

Flight test results for the F-8 digital fly-by-wire aircraft control sensor analytic redundancy management technique

Abstract: This paper reviews the formulation and flight test results of an algorithm to detect and isolate the first failure of any one of twelve duplex control sensor signals being monitored. The technique uses like-signal differences for fault detection while relying upon analytic redundancy relationships among unlike quantities to isolate the faulty sensor. The fault isolation logic utilizes the modified sequential probability ratio test, which explicitly accommodates the inevitable irreducible low frequency errors present in the analytic redundancy residuals. In addition, the algorithm uses sensor output selftest, which takes advantage of the duplex sensor structure by immediately removing a highly erratic sensor from control calculations and analytic redundancy relationships while awaiting a definitive fault isolation decision via analytic redundancy. This study represents a proof of concept demonstration of a methodology that can be applied to duplex or higher flight control sensor configurations and, in addition, can monitor the health of one simplex signal per analytic redundancy relationship.

Remote control system

Abstract: PURPOSE:To ensure the fault detection of the down-circuit as well as the presumption of the faulty area, by transmitting the signals from several slave stations to the master station via the up-circuit and then connecting the slave station alternately to the main down-circuit and the secondary down-circuit for reception of the signals from the master station. CONSTITUTION:The odd-numbered slave stations 121, 123...12n-2, 12n are connected to main down-circuit 16; while even-numered slave stations 122, 124...12n-3, 12n-1 are connected to secondary down-circuit 18 respectively. And these slave stations receive the signals from the master station each. And if the disconnection of circuit 18 occurs between slave stations 12n-5 and 12n-3, master station 11 can knows the fault of circuit 18 from the fact that no answer is given from slave stations 12n-3 and 12n-1. At the same time, the signals of the circuit disconnection are delivered from slave stations 12n-3 and 12n-1 based on the fact that the signal of a prescribed level does not exist in receiving circuit 121. And logic part 126 delivers the switching command of switch 123 to connect slave stations 12n-3 and 12n-1 to circuit 16. Thus the communication is started again between the master station and the slave stations. Slave stations 12n-3 and 12n-1 send the information of the disconnection of circuit 18 to have the confirmation at the master station.

On-line power plant signal validation technique utilizing parity-space representation and analytic redundancy. Final report. [PWR]

Abstract: In this study a technique utilizing parity-space representation (an efficient method for finding a consistent subset of redundant measurements) and analytic redundancy (relationships among dissimilar variables) is designed for use in a real-time digital-computer-based system to isolate sensor and non-sensor component failures in the steam generator and feedwater subsystem of a reference nuclear power plant. The developed method differs substantially from global approaches requiring high-dimensional models. By employing previously validated variable estimates and relying upon physically adjacent information for fault isolation, inherently simple models can be used. Thus the developed method is easily segmented in a plant-wide application and is ideally suited to parallel computer processing.

Random Fault Analysis

Abstract: A method is presented for performing rapid Test Pattern Evaluation (TPE) using classical statistical analysis This method is applicable regardless of the types of faults being considered, the likelihood of the fault occuring, or the technique used for fault simulation A subset of the complete fault list is selected using random sampling techniques, and the fault coverage (percentage of faults detectable by the given test pattern) is estimated and confidence limits about this estimate are given This technique is useful for LSI as well as VLSI Test Pattern Evaluation in that only a small subset of the total fault list need be analyzed to determine the fault coverage within a few percent

Methodology for measurement of fault latency in a digital avionic miniprocessor

Abstract: Using a gate level emulation of a typical avionics miniprocessor, fault injection experiments were performed to (1) determine the time to detect a fault by comparison monitoring, (2) forecast a program's ability to detect faults and (3) validate the fault detection coverage of a typical self test program. To estimate time to detect, six programs ranging in complexity from 6 to 147 instructions, were emulated. Each program was executed repetitively in the presence of a single stuck at fault at a gate node or device pin. Detection was assumed to occur whenever the computed outputs differed from the corresponding outputs of the same program executed in a nonfaulted processor. Histograms of faults detected versus number of repetitions to detection were tabulated. Using a simple model of fault detection, which was based in an analog with the selection of balls in an urn, distributions of time to detect were computed and compared with those obtained empirically. A self test program of 2,000 executable instructions was designed expressly for the study. The only requirement imposed on the design was that it should achieve 95% coverage. The program was executed in the presence of a single stuck-at fault at a gate node on device pin. The proportion of detected faults are tabulated. In all experiments faults were selected at random over gate nodes or device pins.

The user’s Role in Automated Fault Detection and System Recovery

Abstract: Systems whose failure can cause loss of life or large economic loss need to be tolerant to faults (i.e. faults in system hardware, software, and procedures). Examples of such systems include airplane autopilots in the automatic landing mode, electricity utility power generation plants, and telephone electronic switching systems (ESS). Such systems are characterized by high reliability; they fail infrequently and recover quickly when a fault does occur. The user usually cannot respond fast enough if and when a fault is detected. Even if he could respond, his proficiency would not be high because the fault occurs infrequently.

Fault Diagnosis with Imperfect Tests

Abstract: This paper derives a minimum s-expected cost sequence of built-in-tests (BITs) which will partition modular equipment into mutually exclusive groups of modules. After a fault in the equipment, one of these groups will be identified by a BIT diagnostic subsystem as the group which contains a faulty module. The BITs are imperfect in the sense only that they might not detect all of the possible faults in the equipment; they are perfect in the sense that fault indications are never false. The proportion of faults detectable by each BIT is known. Both the cost of a BIT and the probability that a BIT will pass or fail are functions of which modules are tested. A recursive algorithm is developed which determines a sequence of BITs with a minimum s-expected life-cycle cost. The recursive algorithm is applied to a 4-element numerical example. The algorithm has neither been proved nor implemented for a computer.

Test-Experiments for Detection and Location of Intermittent Faults in Sequential Circuits

Abstract: Practical solutions have not been obtained from the previous papers addressing the problem of testing intermittent faults in sequential circuits. Existing methods are only suitable for small sequential circuits. This correspondence presents a new technique to design test-experiments for intermittent faults which can conveniently be used for relatively more complex synchronous sequential circuits.

Fault detecting system for signal bus

Abstract: PURPOSE:To realize the fault detection for the address bus, by transmitting periodically the specific signal for the test of the address bus to the address bus from CPU and then testing the specific signal through the test circuit. CONSTITUTION:When CPU transmits the signals of AB0=AB2-AB14=''1'' and AB1=AB3-AB15=''0'' to address bus AB0-15, the outpts of exclusive logic sum circuit GTO are all ''1'' along with output A of NAND circuit GT1 turnd to ''0'' each. And output C of mono-multi M/M to which above-mentioned outputs are supplied turns to ''1''. Then when CPU transmits the signals of AB0-AB2-AB14= ''0'' and AB1-AB15=''1'' to the same bus, the outputs of exclusive logic sum circuit GT2 are all ''1''. And output B of inverter GT4 turns to ''1'' via NAND circuit GT3. Accordingly, the output of NAND circuit GT5 turns to ''0'', and timer circuit TM is reset. Thus the specific signal is transmitted periodically to bus AB0-15 from CPU. As a result, the fault of the bus can be detected in case the output exists in circuit TM.

Synchronism fault detection system

Abstract: PURPOSE:To bracket a fault point instantaneously by monitoring a synchronism fault through an in-use device and a stand-by device which is made hot simultaneously, and collating their results with each other. CONSTITUTION:Information from an incoming-side circuit Wi is passed through the multiplexing part 2, channel 3, and demultiplexing part 4 of an in-use system, and sent out to an outgoing-side circuit Wo through a switching circuit 5. At this time, the multiplexing part 2', channel 3', and demultiplexing part 4' of a stand-by system are made hot. Multiprocessing synchronizing devices 10 and 10' are connected to the channels 3 and 3' to detect a synchronism fault; pieces of fault information are collated with each other by a collating circuit 11, and the outputs of the demultiplexing parts 4 and 4' are collated with each other by a collating circuit 12. When an exchange is normal and a fault occurs on the transmission line, outputs of the circuits 11 and 12 are both 0, and the devices 10 and 10' judge in which circuit the fault occurs from a time slot number. When the transmission line is normal and a fault occurs to either of the channels 3 and 3', the outputs of the circuits 11 and 12 are 1. When a fault occurs between either of channels 3 and 3' and the output side, the output of the circuit 11 is 0 and the output of the circuit 12 is 1.

Fault detection system of mobile radio communication system

Abstract: PURPOSE: To diagnose a fault of a mobile station transmission connection controlling channel (A.CH) system totally and automatically when the frequency of the transmission of a mobile station is low, by monitoring the reception input electric field information and demodulated signal of an (A.CH) receiver. CONSTITUTION: A test-call monitoring control part 15 monitors electric field information from an (A.CH) transmitter 12 all the time and starts a fault diagnosis of the A.CH in a time zone when transimission from a mobile station is less. Firstly, the control part 15 performs transmission control with a testing mobile station 16 through a connection line 24. The transmitted signal is demodulated by the A.CH receiver 13 of a radio base station 1 and sent to a center station 7 to perform the transmission connection. The center station 7 transmits an indication signal for a path channel to the A.CH transmitter 12 through a line 18. Once the transmitter 12 sends out said indication signal to the testing mobile station 16, the station 16 supplies the indication signal to the test call monitoring control part 15 through a line 24, thereby judging the normality of the A.CH system. COPYRIGHT: (C)1982,JPO&Japio

CPU coverage evaluation using automatic fault injection

Abstract: A method has been developed for evaluating central processing unit (CPU) coverage by automatically injecting faults into actual CPU hardware while it is executing relevant test software. A special hardware test fixture is used which contains the CPU under evaluation, program and data memory, and a terminal interface. The test fixture is connected to a microcomputer controller and an in-circuit read only memory (ROM) emulator. The faults injected are "stuck-at-1," "stuck-at-0," and open on the appropriate integrated circuit pins, plus the altered state of every microprogram memory bit. The effect of each fault is determined by observing the status of the watchdog monitor. Data reduction is performed after each run on a separate host computer, and summary results are tabulated. N digital avionics systems the central processing unit (CPU) is obviously the dominant functional element, upon which many other elements are dependent in order to perform correctly related interface and control tasks. Normally, there are arrays of system monitors, in both hardware and software, which have an inherently overlapping capability to detect CPU malfunctions. The combined effectiveness of these monitors determines the total CPU fault coverage. However, since many of these monitors are themselves dependent upon CPU operation, there is a critical "topdown" relationship between the monitors which must be considered. In particular, a software monitor is of little subsequent value in the presence of a CPU fault unless one of the two following conditions is present. 1) It is actually executed, and it produces the planned fault detection results, and the fault detection is properly communicated to and acted upon by the ultimate hardware control elements in the system. 2) It causes fault detection elsewhere when it is not executed, and the fault detection is properly communicated to and acted upon by the ultimate hardware control elements in the system. In simplest terms, software monitors depend upon a "rational" CPU; that is, a CPU which is at least able to follow the normal program flow without making addressing or branching errors. If this is not the case, then how can one guarantee that the software monitor is executed? If it is possible to detect the fault of concern without executing the software monitor, then why is the monitor present? The point is that it is critically necessary to have a CPU monitoring scheme which establishes the minimum CPU fault coverage that is required to support all other monitoring activity. Such a monitoring scheme must straddle the hardware-software boundary so that external communication is absolutely guaranteed. In the simple terms introduced in the preceding, such a monitor must be able to detect all faults resulting in "irrational" CPU operation. In most modern digital avionic systems, the monitor which does these things is the so-called "watchdog" monitor (WDM) (or alternately the "heartbeat" or "deadman" timer monitor). The WDM usually operates in relation to the timer

Pseudo fault generator

Abstract: PURPOSE:To vary the timing of fault detection freely by generating a specific fault artificially when an assigned address for reading a micro (mu) instruction reaches preset one. CONSTITUTION:The address of a (mu) instruction generating a pseudo fault is inputted to assigned-address register TAR3 by program PG, and a code expressing the kind of the fault to be generated is also inputted to register DFR11 which indicates in which part of a data processor a pseudo fault should be generated. The address is increased by one address with control storage 1 to read and execute (mu) instructions and when the coincidence between the contents of control storage address register CAR2 and those of TAR3 is found by address coincidence circuit 4, the output signal of circuit 4 sets FF8 via gates 5 and 7 to make decoder 12 effective. The code of DFR11 is decoded by decoder 12 and with this signal, the prescribed pseudo fault is generated. According to contents of TAR3 and DFR11, the pseudo fault is generated at optional timing.