Showing papers on "Fault indicator published in 1987"

Transition Fault Simulation

Abstract: Delay fault testing is becoming more important as VLSI chips become more complex. Components that are fragments of functions, such as those in gate-array designs, need a general model of a delay fault and a feasible method of generating test patterns and simulating the fault. The authors present such a model, called a transition fault, which when used with parallel-pattern, single-fault propagation, is an efficient way to simulate delay faults. The authors describe results from 10 benchmark designs and discuss add-ons to a stuck fault simulator to enable transition fault simulation. Their experiments show that delay fault simulation can be done of random patterns in less than 10% more time than needed for a stuck fault simulation.

Accelerated Transition Fault Simulation

Abstract: This paper presents a new and an effective approach to fault simulation of transition faults in combinational or scan - based logic. An experiment with a set of benchmark circuits demonstrates the efficiency of the approach, achieved by combining a very fast single stuck - at fault simulation algorithm with a quasi - static definition of a transition fault. Tests that cover transition faults are becoming increasingly important as they also provide a cover for most typical transistor stuck - open faults in CMOS.

Multiple-redundant fault detection system and related method for its use

Abstract: A multiple-redundant computer system having multiple computational devices (40a, 40b, 40c) operating in synchronism, multiple voter circuits (30a, 30b, 30c) to provide voted memory reading operations for the devices, and multiple fault detection logic (44a, 44b, 44c) for the detection of failures of the computational devices. Fault status words generated by the fault detection logic are also subject to a voted read by the multiple computational devices, thereby permitting detection of errors in the fault detection logic itself, as well as in the computational devices. The module structure of the invention also permits removal and replacement of circuit modules, each including a computational device and fault detection logic, without disconnecting power from the entire system.

Fault indicator having delayed trip circuit

Abstract: A reset coordinated fault indicator for indicating the occurrence of a fault current in a monitored conductor includes an electrically actuated indicator flag. A trip circuit within the fault indicator impulses the indicator flag from a normal reset-indicating state to a fault-indicating state following the occurrence of a fault current in the conductor. A reset circuit periodically impulses the indicator flag to the reset-indicating state upon restoration of power to the conductor. To preclude simultaneous actuation of the trip and reset circuits and consequent failure of the indicator flag to register a fault, the trip circuit, upon the occurrence of a fault, first actuates the reset circuit to render the reset circuit inoperative, and then actuates the indicator flag to provide a fault indication.

Electronic device with self-monitor for an automotive vehicle

Abstract: A self-monitoring system for an automotive electronc control system such as an engine control system, an electronic anti-skid control system or electronic automatic transmission control system is adapted to check each segment of the electronic control system in order to detect faulty segments. To detect faulty segments, the self-monitor system checks inputs and outputs of the electronic control system. The checked data is stored in a memory which is not erased when the power supply is turned off. The self-monitoring system is associated with another automotive microcomputer which includes a display unit. The other automotive microcomputer is adapted to display the results of the checking operation of the self-monitoring system in response to a display request manually inputted from a manual unit to display identification of the fault segment and/or error condition thereof. The monitor can also be associated with a fault indicator, such as an LED, which is responsive to detection of error in any of the segments to turn on.

Power bus fault detection and protection system

Abstract: A power bus fault detector for detecting faults in a predefined portion of an electrical power bus having at least one phase. Power feed lines are coupled to the predefined portion of the power bus by circuit breakers. Current transformers are used to detect the current flowing through each phase of each power feed line which is coupled to the predefined portion of the power bus. A summer generates a current differential signal for each phase that is equal to the sum of the currents detected by the current transformers. A fault detector generates a trip signal which causes the feed line circuit breakers to disconnect the feed lines from the power bus when a fault is detected in the predefined portion of the power bus. The fault detector includes a detector which detects when the current differential signal in any of the power bus's phases is substantially nonsinusoidal in shape. In a preferred embodiment, the fault detector detects when, for any of the phases, the percentage of time that the magnitude of the current differential signal exceeds a fault cutoff value is greater than the percentage of time that the current differential value exceeds the fault cutoff value for a known minimum fault.

High performance clock system error detection and fault isolation

Abstract: A method and apparatus for fault testing a clock distribution network for A.C. and D.C. faults. The fault testing apparatus includes test latch circuit means and is adapted to initially test for D.C. (stuck) faults and to thereafter continuously monitor a plurality of clock signal lines to detect A.C. clock faults.

Method and device for detecting and localizing faults in electrical installations

Abstract: A method and device for detecting and localizing fault in electrical installations includes performing partial discharge measurements and high-frequency measurements at least at one location in the electrical installation and optionally in all phases, selectively comparing the measurement values with each other and with calibration signals, drawing conclusions from the measurements regarding the location and the type of the fault, selectively continuously and periodically performing the measurements at least at three measuring points while the installation is in operation, simulating the electrical installation in a computer as a high-frequency network, while simulating fault with the signals originating therefrom at the measuring points, comparing any measurement values which indicate fault with the simulated signal values for different fault types and fault locations, and determining the type and location of the fault from the simulated signal values which best agree with the measurement values and from the corresponding simulated fault.

Fault diagnosis system for automotive electronic devices

Abstract: A fault diagnosis system for automotive electronic devices, suitable for use in an automobile having at least one electronic device which is provided with a sensor for sensing the state of operation of at least one automotive part and an actuator for controlling the operation of the automotive part in accordance with the state sensed by the sensor, the electronic device having a self-diagnosis function for detecting any fault in said sensor or said actuator and for storing data concerning the detected fault. The fault diagnosis system has a diagnosis tester which includes an input circuit for receiving a fault detection signal which is produced as a result of self-diagnosis performed by the self-diagnosis function of said electronic device, a display control circuit for converting the fault detection signal received by the input circuit into a display control signal, a display for displaying, in accordance with said display control signal, data representing the sensor or said actuator having the fault, and a sound generating device receiving the display control signal for generating an aural alarm in response to a fault.

Motor controller for pumping units

Abstract: A method and apparatus for controlling the operation of an oil well pumping unit in which the prime mover is a polyphase AC electric motor. The system comprises means for generating a plurality of signals representative of motor fault parameters including a motor winding overtemperature fault, undervoltage fault, and a phase imbalance fault. Upon occurence of a fault, a contactor in the motor supply leads is open to shut down the motor. After such shutdown because of undervoltage or phase imbalance faults the fault parameters are continuously scanned and once the fault has been cleared the motor is restarted. Where motor shutdown occurs because of an over temperature fault, the motor is maintained in a latched off shut down condition until an operator implemented reset occurs. An accessible counting memory is provided having separate registers for each of the fault conditions.

Phase controller for processing current and voltage faults

Abstract: A power supply system for processing current and voltage faults is disclosed. Each phase of a first power source (12) and each phase of a second power source (28) has a pair of switches (60, 64) for controlling the conduction of current from the phase of the power source to a phase load (29). In each of the phases of the first power source (12), a first switch (60) is controlled by a first control signal which has a high level when a voltage fault or current fault condition does not exist. When either a voltage fault or a current fault condition exists, the first switch (60) is turned off. The second switch (64) is turned on by a second control signal during a determination of whether a current fault exists. Furthermore, a logic network causes the first control signal to assume the second level in response to any one of an RMS over/under voltage fault, an instantaneous overcurrent fault, an I2 t fault, or an instantaneous voltage fault occurring in the phase to which the switches are connected or in any one of the other phases in the first power source. Upon the detection of a voltage fault condition, the first power source (12) is disconnected from the load and a second power source is connected to the load. All of the phases of the first power source are disconnected either immediately in response to the detection of a fault in any one of the phases or, alternatively, the phase with the fault is immediately disconnected and the remaining phases without a fault are disconnected at the zero current crossing points of the AC signal of the phases. The phases of the second source are connected at a point when the voltage of the phase is zero.

Monitoring device for the flashing indicator signalling system of motor vehicles

Abstract: In a monitoring device for the flashing indicator signalling system of motor vehicles, having a monitoring resistor in the flashing light circuit, having a first device for monitoring a first flashing light load, which device actuates a first fault indicator, and having a second device for monitoring a second flashing light load, which device actuates a second fault indicator, according to the invention the first and the second device are combined to form a common device. This common device has a comparator which serves to compare the voltage drop at the monitoring resistor with a threshold value. Furthermore, the common device has a timer which measures the time period in which the voltage drop is greater than the threshold value. The fault indicators can be actuated as a function of the measured time period. As a result, it is possible to monitor various values of flashing lights simultaneously on one device in a simple and cost-effective manner.

The Effects of Latent Faults on Highly Reliable Computer Systems

Abstract: Latent faults represent a potential obstacle in the synthesis of highly reliable digital computer systems. A simulation of an NMR redundant processor system was constructed using a gate level simulation package. The ability of each digital processor to react to randomly induced stuck-at faults is measured, and the amount of time it took the processor's control program to propagate faults to an output was recorded. These propagation times represent the latency times of the faults. The effect of fault latency in degrading system reliability is explored.

Fault-location algorithm for multiphase power lines

Abstract: Improved mathematical models of transmission lines are used to develop a fault location method which copes with high-frequency transients. The telegraph equations used for a line model are solved by the method of characteristics using voltage and current samples as boundary conditions taken at one end of the line within the first few milliseconds of fault inception. Estimates of voltage and current profiles for the entire length of the transmission line during the fault are obtained. Criteria for fault location are based on a formulation involving these voltage and current estimates. For fault location on multiphase systems the concept of modal analysis is used in enhancing the fault-locating capability of this algorithm.

Fault diagnostic apparatus for electric appliance

Abstract: A fault diagnostic apparatus for a device subject to a plurality of predetermined fault conditions. The apparatus includes a fault detector for automatically detecting the occurrence of any of the plurality of fault conditions and an indicating circuit for indicating the occurence of only specific one of the plurality of fault conditions manually designated by an operator.

Efficient fault diagnosis in analogue circuits using a branch decomposition approach

Abstract: A branch decomposition approach for fault diagnosis in analogue circuits is presented. Two fault models for the fault simulation of operational amplifier circuits are also proposed. The method uses linear fault diagnosis (FD) equations based on Kirchhoff's current law and nodevoltage measurements under the desired current excitations. The circuit is divided into subnetworks and appropriate interconnections. The checking of the consistency of the FD equations using nominal element values and the measured node voltages leads to the location of the faults in the circuit. The procedure can be applied to linear or nonlinear circuits for the location of single and multiple faults. Demonstrative examples of passive and active circuits are given to show the effectiveness of the proposed method.

Fault point locating method, fault point resistance measuring method, and impedance to fault point measuring method, and apparatus therefor

Abstract: This invention relates to a method for locating a fault point in a two-terminal system transmission line, a method for measuring impedance to the fault point at a three-terminal system transmission line, and methods for measuring the fault point therefor, and locators and measuring apparatus for putting these methods in practical use. It is utilized that, when a fault point current is made reference, the sine com­ ponent of voltage at the apparatus installation point is equal to the sine component of impedance drop to the fault point therefrom, and that a phase difference between the com­ ponent of current flowing in the fault point from the apparatus installation side end and that of a fault point current of the sum of the components of current flowing from the apparatus installation end and of current flowing from the other end to the fault point are substituted into the equation representing the above relation, thereby enabling the fault location, fault point resistance measurement and impedance measurement to the fault point to be measured without using the voltage and current data of the other end.

Fault state reporting system

Abstract: PURPOSE: To quicken the detection of fault occurrence by providing a function generating a fault status report where an instantaneous failure status of each communication line and each node, a fault status based on the result of monitor within a prescribed time while being roughly classified depending on the fault status and a function sending the report to a network management center to each node. CONSTITUTION: Multiplexers 1,2 are connected to a ground high speed digital line 4 by a satellite line 7. The fault information at the instantaneous time and withinprescribed time collected by the multiplexer 1 is classified depending on the fault state and communicated to the center 11 in a form of a status word, for example. Moreover, the multiplexer 1 is provided with a function monitoring the state of the communication line and the multiplexer 1 itself at a sampling time interval, a function generating the fault status report comprising the result of monitor of a specified time and the instantaneous value at present in a form of status word, for example, aud a function returning the report in a form of the status word in response to the polling from the center 11. Thus, the time till the detection of fault occurrence is shortened. COPYRIGHT: (C)1988,JPO&Japio

Distance measuring relay for line faults

Abstract: In a short-circuit distance relay for protecting a single-channel power transmission system with power supplies installed at two ends thereof, when there exists any resistance at a fault point on the power transmission line, an error is induced in measurement of the distance up to the fault point by a voltage drop component flowing through the fault-point resistance from the remote-end power supply. In order to eliminate such error in measuring the distance, the relay of this invention computes the impedance up to the fault point from the information including a positive-phase voltage and a positive-phase current in a normal state of the power transmission system, and also a positive-phase voltage, a positive-phase current and a negative-phase current in a faulty state of the system, whereby the fault-point resistance is rendered unconcerned with the distance to consequently avert the measurement error.

Device for indicating machine faults and production data on polygraphic machines

Abstract: The invention relates to an indicator device for signalling machine faults and production data on polygraphic machines. The aim of the invention is to provide a device of this type which makes it possible to recognise this information more simply and independently of the station of the operating personnel. The technical object of the invention is, therefore, to design the device in such a way that faults and imminent failures of operating units can be recognised in good time from a plurality of stations of the operating personnel and the location of the fault can be determined easily and, moreover, the production data can be called up in a controlled manner from these stations. The object is achieved in that the indicator device consists of an indicator board allowing a selective indication, triggerable by remote control, of the individual production data and an automatic indication of faults, and the indicator board is arranged pivotably. Advantageously, the outlay is minimised by arranging on the indicator board a number of segmental modules necessary for the longest production-data or fault information item to be indicated.

Software Implemented Fault Insertion: An FTMP Example.

Abstract: This report presents a model for fault insertion through software; describes its implementation on a fault-tolerant computer, FTMP; presents a summary of fault detection, identification, and reconfiguration data collected with software-implemented fault insertion; and compares the results to hardware fault insertion data. Experimental results show detection time to be a function of time of insertion and system workload. For the fault detection time, there is no correlation between software-inserted faults and hardware-inserted faults; this is because hardware-inserted faults must manifest as errors before detection, whereas software-inserted faults immediately exercise the error detection mechanisms. In summary, the software-implemented fault insertion is able to be used as an evaluation technique for the fault-handling capabilities of a system in fault detection, identification and recovery. Although the software-inserted faults do not map directly to hardware-inserted faults, experiments show software-implemented fault insertion is capable of emulating hardware fault insertion, with greater ease and automation.

Fault point location system for three-terminal power transmission system

Abstract: PURPOSE: To speed up fault restoration by locating a fault position occurring on a power transmission line in a three-terminal power transmission system according to voltage quantities and current quantities of respective phases after a fault detected at respective terminals of the power transmission line. CONSTITUTION: Terminal devices A1, B1, and C1 are provided at an A terminal, a B terminal, and a C terminal, voltage quantities and current quantities measured here are sent as data to a center device D, and used to perform vector arithmetic by a prescribed location arithmetic expression, thereby locating a fault point position. Namely, voltages and currents at the respective terminals are sampled and gathered on one place to find voltage drops per unit length of the power transmission system between each terminal and a branch according to the current data from the respective terminals, thereby deciding the section where the fault point is present by using those voltage drops, respective voltage data, and the distances between the terminals and the branch. Then the distance from the terminal in the fault section to the fault point is calculated from the integral value of the voltage drop per unit from the terminal of the fault section and fault section distance. COPYRIGHT: (C)1988,JPO&Japio

Three-valued diagnosable systems: Diagnosability, optimal design and fault identification algorithm

Abstract: A three-valued model for computer system diagnosis is proposed in this paper. A subsystem is regurded as composed of two components, a task processor and a communication processor. Accordingly, subsystem faults are classified as type 1 or type 1/2 faults, representing subsystem faults with communication processors being faulty or those with communication processors being fault-free, The concepts of virtual tests andt 1 /t 1/2 fault diagnosis are introduced. Andt 1 /t 1/2 fault diagnosis with centralized control and that with distributed control are studied respectively. The problems addressed here include diagnosability, optimal design and fault identification algorithm. The results show clearly thatt 1 /t 1/2 fault diagnosis can afford to identify significantly more faults thant-fault diagnosis under the same structural constraint.

A new approach of stuck-at fault simulation for synchronous digital systems

Abstract: A new approach is proposed for stuck-at fault simulations. Stuck-at fault models in the approach are developed via the component connection model. Based on the approach, a simulation program is designed. A combinational logic circuit is simulated and the test sets are generated using the program.

Fault diagnosing device for electronic device

Abstract: PURPOSE: To find a faulty component speedily by utilizing a knowledge base when receiving fault information and also utilizing a test executing means and a component replacing means to diagnose a fault. CONSTITUTION: If a fault occurs in an electronic device 2, a fault detecting means 5 detects the fault and a diagnostic part 13 analyzes its fault information by using the knowledge base 12 to recognize its symptoms, and considers that all function blocks included in the path of the flow of signals which cause the symptoms possibly are in an initial false fault range. The diagnostic part 13 conducts 6 a test by which a part causing the fault and a part causing no fault in the false fault range are demarcated or replaces 7 components including function blocks in the false fault range, thereby narrowing down the false fault range by interpreting the execution result. Thus, the false fault range is reduced more and the fault is restored by replacing a component relevant to the fault eventually. COPYRIGHT: (C)1988,JPO&Japio

Fast Fault Coverage Estimation at the Transistor Level

Abstract: One of the most time consuming activities in the design of VLSI systems is the determination of fault coverage for a given test set. This information is crucial in the generation of test patterns, in order to ensure a system is adequately exercised. Fault simulation may be employed to determine fault coverage, but the time required to perform this rises, at best, as the square of the number of gates/devices. Efforts have been directed at reducing the computation time required for full fault simulation, including the use of testability analysis programs, and statistical fault estimation. This paper is concerned with the latter, in particular, the estimation of fault coverage from the results of fault-free simulation. Existing approaches carry out this analysis from the gate level without considering how the gates are constructed. After reviewing gate level approaches, this paper considers transistor level descriptions and it is shown how some structures (notably those involving pass transistors) cannot be modelled satisfactorily at the gate level, and require special methods to arrive at controllability and observability metrics for circuit nodes. Expressions are developed for the estimation of controllability, observability and fault detection probabilities for both switch logic and active gate structures, based on simple counting operations carried out during fault-free simulation. It is shown how an existing switch level simulator is very easily modified to allow rapid fault information to be obtained.

Fault locating system

Abstract: PURPOSE: To confirm a high-order fault section from a low-order network coupler and to speed up the restoration of a fault by discriminating the presence or absence of a receiving carrier detection during the fault locating packet transmittion with a fault locating device and whether the timing in which the receiving carrier is turned off is present before the completion of the trouble searching packet or present after it. CONSTITUTION: On a fault locating system, a high-order network star coupler 20, a low-order class star coupler 6 and a bidirectional repeater 11 are arranged, and a fault locating device 42 is connected to the star coupler 6 by a low-order network incoming fiber 5 and a low-order network fiber 31. From a fault locating packet generating device 43 of the device 42, a fault locating packet is inputted to a transmitter 44 for locating a fault and the packet of a wavelength λ2 is outputted to the fiber 5 by a light-emitting element 43. The locating packet is repeated through the coupler 6 to a high-order network with the repeater 11 and the output to the low-order network is interrupted by a repeating side control part 16. A packet length supervising controller 47 detects the duration after the specified time from the reception starting of a low-order network side receiver 13 and confirms the fault section. COPYRIGHT: (C)1988,JPO&Japio