Showing papers on "Field-programmable gate array published in 1991"

Chortle-crf: Fast technology mapping for lookup table-based FPGAs

Abstract: A new technology mapping algorithm for lookup tablebased Field Programmable Gate Arrays (FPGA) is presented. The major innovation is a method for choosing gate-level decompositions based on bin packing. This approach is up to 28 times faster than a previous exhaustive approach. The algorithm also exploits reconvergent paths and replication of logic at fanout nodes to reduce the number of lookup tables in the circuit. The new algorithm is implemented in the Chortle-crf program. In an experimental comparison Chortle-crf requires 14 YO fewer lookup tables than Chortle [Fran90] and 10 ~o fewer lookup tables than mis-pga [Murg90a] to implement a set of benchmark networks. Chortle-crf can also implement a network as a circuit of Xilinx 3000 series Configurable Logic Blocks (CLBS). To implement the benchmark networks as circuits of CLBS Chortle-crf requires 12 70 fewer CLBS than mis-pga and 22 % fewer CLBS than XNFOPT [Xili89]. In these experiments Chortle-crf waa an average of 68 times faster than mis-pga and 30 times faster than XNFOPT. 1

Flexibility of interconnection structures for field-programmable gate arrays

Abstract: The relationship between the routability of a field-programmable gate array (FPGA) and the flexibility of its interconnection structures is examined. The flexibility of an FPGA is determined by the number and distribution of switches used in the interconnection. While good routability can be obtained with a high flexibility, a large number of switches will result in poor performance and logical density because each switch has significant delay and area. The minimum number of switches required to achieve good routability is determined by implementing several industrial circuits in a variety of interconnection architectures. These experiments indicate that high flexibility is essential for the connection block that joins the logic blocks to the routing channel, but a relative low flexibility is sufficient for switch blocks at the junction of horizontal and vertical channels. Furthermore, it is necessary to use only a few more routing tracks than the absolute minimum possible with structures of surprisingly low flexibility. >

Improved logic synthesis algorithms for table look up architectures

Abstract: The authors address the problem of synthesis for a popular class of programmable gate array architecture-the table look-up architectures. These use lookup table memories to implement logic functions. The authors present improved techniques for minimizing the number of table look up blocks used to implement a combinational circuit. On average, the results obtained on a set of benchmarks are 15-29% better than results obtained by previous approaches. >

A CMOS field-programmable analog array

Abstract: The design details and test results of a field-programmable analog array (FPAA) prototype chip in 1.2- mu m CMOS are presented. The analog array is based on subthreshold circuit techniques and consists of a collection of a homogeneous configurable analog blocks (CABs) and an interconnection network. Interconnections between CABs and the analog functions to be implemented in each block are defined by a set of configuration bits loaded serially into an onboard shift register by the user. Macromodels are developed for the analog functions in order to simulate various neural network applications on the field-programmable analog array. >

Technology mapping of lookup table-based FPGAs for performance

Abstract: A novel technology mapping algorithm that reduces the delay of combinational circuits implemented with lookup-table-based field-programmable gate arrays (FPGAs) is presented. The algorithm reduces the contribution of logic block delays to the critical path delay by reducing the number of lookup tables on the critical path. The key feature of the algorithm is the use of bin packing to determine the gate-level decomposition of every node in the network. In addition, reconvergent paths and the replication of logic at fanout nodes are exploited to further reduce the depth of the lookup table circuit. For fanout-free trees the algorithm will construct the optimal depth K-input table circuit when K is less than or equal to 6. >

Xmap: A technology mapper for table-lookup field-programmable gate arrays

Abstract: Conversion from BLIF to If-then-else DAGS This paper presents a new algorithm, Xmap, for doing mapping from multi-level logic to field-programmable gate arrays based on table-lookup gates, such as those used in the Xilinx chip. The algorithm is based on an if-then-else DAG represen- tation for the functions. The technology mapper differs from previous mappers in that the circuit is not decomposed into fan-out-free trees. The Xmap algorithm uses 7% fewer cells than Chortle, 11% fewer than misII, and 14% fewer than mis-pga, and is 4.5 times faster than Chortle, 17 times faster than misII, and at least 150 times faster than mis-pga.

Preprogramming testing in a field programmable gate array

Abstract: A field programmable gate array integrated circuit which has numerous features for testing prior to programming the antifuses in the integrated circuit is provided. The circuits used to program the antifuses are also used for much of the preprogramming testing. The functionality of continuous series transistors and latch logic blocks may be tested together with the continuity of their programmable connections. Programmable input/output buffer circuits and clock circuits which set the desired clock network paths may be tested with signals on a serial scan path which passes through the input/output buffer circuits and clock circuits. Process characterization tests without the requirement of high-speed test equipment are also provided.

Technology mapping for electrically programmable gate arrays

Abstract: We describe a new approach for technology mapping of electrically programmable gate arrays (EPGAs). These are arrays of uncommitted modules, where the personalization is achieved by fuselantifuse technology and can be modeled by stuck-at and/or bridging inputs. We present a matching algorithm that determines whether a portion of a combinational logic circuit can be implemented by personalizing a module. The algorithm has the advantage of considering the entire library of functions that can be implemented by the module without resorting to an explicit enumeration. The benefits are an increased efficiency in technology mapping, as well as portability to different types of electrically programmable gate arrays. Experimental results on standard benchmarks are reported.

Technology mapping for a two-output RAM-based field programmable gate array

Abstract: The authors present a new approach for performing technology mapping onto field programmable gate arrays (FPGAs). They consider one class of FPGAs, based on two-output five-input RAM-based cells, that are used to implement combinational logic functions. A heuristic algorithm is described for technology mapping that performs a decomposition of the circuit in the FPGA primitives, driven by the information on logic functional sharing. The authors have implemented the algorithm in the program Hydra. Experimental results shows an average of 20% to 25% improvement over other existing programs in mapping area and 67-fold speedup in computing time. >

Amap: A technology mapper for selector-based field-programmable gate arrays

Abstract: This paper presents two algorithms for doing mapping from multi-level logic to selector-based field-programmable gate arrays, such as the Actel chip. The gate counts and CPU time are compared with two previous mappers for these architectures: misI1 and mis-pga. The Amap algorithm use 6% fewer cells than mid1 and only about 8% more cells than the best achieved by mis-pga, and is at least 25 times as fast as mid1 and at least 586 times as fast as mis-pga. The XAmap algorithm is slightly slower, and not quite as effective.

Field programmable gate array

Abstract: A FPGA matching the organization and performance of mask programmable gate arrays is presented. The core array is organized into rows of continuous series transistors (CSTs) and rows of small latch/logic blocks. The source/drains and gate of each of the transistors are connected to line segments. The input and output terminals of the blocks are also connected to line segments. Programmable antifuses are located at the intersections of the line segments, which also include others for power and routing purposes. The FPGA can be efficiently configured into a user's application with the flexibility of the CSTs and the efficiency of the latch/logic blocks, which may also be configured into RAM arrays.

Programmable interconnect device and method of manufacturing same

Abstract: A programmable interconnect device particularly suitable for field programmable ROM, field programmable gate array and field programmable microprocessor code, includes an intrinsic polycrystalline antifuse dielectric layer.

Borg: a reconfigurable prototyping board using field-programmable gate arrays

Abstract: Field-Programmable Gate Arrays (FPGA) provide a medium to accelerate the process of prototyping digital designs. For designs with multiple FPGAs that need to be connected together, the bottleneck is now the process of wire-wrapping, bread-boarding, or (worse) the construction of a printed circuit board, which cannot be carried out until all FPGA designs are routed. It is because locking or preassigning I/O blocks often prevent FPGA placement/routers from completing the routing.\\ We exploit the reprogrammability of FPGAs and use them for routing. To experiment with the idea, we constructed a PC-based prototyping board that contains two ``user'''' FPGAs, two routing FPGAs, and an FPGA that serves as glue logic to the PC bus. To facilitate the design process using the new prototyping board, we developed algorithms and tools that automatically configure the routing FPGAs. We describe the options that we have examined during the development of this board, and how we arrive at some design decisions. The toolset, user FPGAs, and the routing FPGAs and the reprogammability of the FPGAs serve to further reduce the time/cost of constructing prototypes using FPGAs.

A reconfigurable data path processor

Abstract: A configurable data path processor is presented which can be modified to optimize performance. FPGA, PLA and PAL devices provide a great amount of flexibility to realize arbitrary control functions. The new processor is specifically designed for arbitrary data path operations and can be dynamically reconfigured. >

Empirical evaluation of multilevel logic minimization tools for a field-programmable gate array technology

Abstract: We examine empirically the performance of multi-level logic minimization tools for a lookup table-based Field-Programmable Gate Array (FPGA) technology. The experiments are conducted by using the university tools *misII* for combinational logic minimization and *mustang* for state assignment, the industrial tools *xnfmap* for technology mapping, and *apr* for automatic placement and routing. We measure the quality of the multi-level minimization tools by the number of *routed* configurable logic blocks (CLBs) in the FPGA realization. We report three results: a) we have developed a new system to support rapid prototyping using FPGAs, b) there is a linear relationship between the number of literals and the number of *routed* CLBs, and c) in all but one of the 31 *MCNC-89* benchmark finite state machines, one-hot state assignment resulted in substantially less CLBs than any other state encoding method. These results are useful to those who prototype a design in FPGAs, and then transfer the design to a different technology (e.g., CMOS standard cell). It provides valuable information on the difference in performance of a design realized in different technologies.

Array architecture for ATG with 100% fault coverage

Abstract: Discusses an array architecture, circuitry and methodology for the automatic generation of test vectors. The architecture has been implemented in a mask programmed version of an antifuse based FPGA. The architecture provides 100% controllability and observability of each node in the circuit. This allows the automatic generation of test vectors with 100% fault coverage independent of the design implemented in the array circuit. In addition to architecture and circuit implementation details, the paper discusses the ATG generation methodology and algorithms, circuit overhead for the test features as well as test times and results. >

Field programmable gate array key to reconfigurable array outperforming supercomputers

Abstract: In order to solve the problem of mapping the human genome and other similar problems, the Supercomputing Research Center (SRC) developed SPLASH, a reconfigurable linear logic array. The SPLASH system gives a Sun workstation better than supercomputer performance on certain classes of problems. SPLASH's performance can surpass that of the Cray 2 by a factor of 325. Field-programmable gate arrays (FPGAs) were used to build SPLASH, which is efficient like a specialized board, yet flexible like a supercomputer. The SPLASH system consists of software and hardware which plugs into two slots of a Sun workstation. The types of problems SRC is able to solve with SPLASH, why traditional solutions were not practical, and how FPGA technology allowed SRC to build SPLASH are discussed. >

Automatic synthesis of Boolean functions on Xilinx and Actel programmable devices

Abstract: Synthesis methods for two types of programmable devices Xilinx and Actel are presented The optimization criterion is first the critical path of the final circuit and secondly the number of devices required to implement the function The methods consist of an adequate factorization step followed by a mapping adapted to each target >

TRIPTYCH: A New FPGA Architecture

Abstract: Existing FPGA architectures can be classified along two dimensions: reprogrammable vs. one-time programmable and general-purpose vs. domain specific. The most challenging class of FPGA architectures to design is the reprogrammable, general-purpose FPGA, of which Xilinx is the most wellknown example. In this paper we describe Triptych, a new FPGA architecture that addresses two problems of current reprogrammable FPGAs: the large delays incurred in composing large functions and the strict division between routing and logic resources. Our studies indicate that Triptych is more areaefficient than current architectures and has comparable delay characteristics for a large range of circuits that include both data-path elements and control logic.

A large scale FPGA with 10 K core cells with CMOS 0.8 mu m 3-layered metal process

Abstract: A large-scale FPGA (field-programmable gate array) that contains 10 K core cells is described. The core cell, a programmable logic module, consists of a two-input NAND gate, a latch circuit, and bus drivers. The function of one core cell is estimated to be equivalent to four NAND gates. As a result, the FPGA integrates a total of 40 K gates. Configuration data are stored in SRAMs on the device. A booster circuit on the chip supplies higher voltage to reduce on-resistance of the switch elements to ensure high-speed operation. This FPGA has two programming modes, the BFR (boot from ROM) mode, in which the FPGA accesses outer nonvolatile memory devices, and the CPU mode, which is controlled by a CPU as a peripheral device. A probe system is implemented on the device to read the output signal of each core cell to realize swift debugging of configured circuits. >

A programmable real-time systolic processor architecture for image morphological operations, binary template matching and min/max filtering

Abstract: Mathematical morphology, min/max, and binary template matching operations can form a sufficiently complete image analysis system for a broad range of industrial/robotics applications. The authors present a bit-level systolic pipeline architecture for performing these operations in real time. The architecture is obtained by mapping algorithms to array structures, and it is flexible with respect to kernel sizes and processing stages. The architecture is best suited for high clock frequency and will have easy and low-cost implementation with FPGAs (standard chips) or custom ASICs (application-specific integrated circuits). >

Adaptive hardware becomes a reality using electrically reconfigurable arrays (ERAs)

Abstract: Reconfigurable systems-which modify their operation to adapt to prevailing conditions-promise new and exciting design concepts for the 1990s. Adaption, to date, has primarily been the domain of software, but new hardware techniques of logic design using RAM based silicon open up significant benefits. The author discusses how the Electrically Reconfigurable Arrays (ERAs) can be used in adaptive hardware systems. The generic name of SRAM based products such as the ERA is Field Programmable Gate Arrays (FPGAs). Key features to look for in FPGAs for adaptive hardware applications are speed and flexibility of reconfiguration.

A methodology for programmable logic migration to ASICs including automatic scan chain insertion and ATPG

Abstract: Describes a methodology to migrate field programmable logic (FPL) to a gate array or standard cell ASIC with automated schematic translation, functional verification, static timing analysis, and test program generation. The input to the migration flow is the FPL netlist. The translation software replaces existing flip-flops with equivalent scan flip-flops and connects a scan chain. Automatic test pattern generation (ATPG) software then produces high fault coverage test patterns. Timing reports and workstation schematics of the ASIC are available post migration for timing verification and device simulation before manufacturing. This methodology reduces the execution time for FPL migration from man-months to man-days. >

Xilinx-the third generation

Abstract: Before delving into the advantages offered to the designer by the new 3rd generation 4000 series from Xilinx, a brief discussion of the alternatives available to the logic designer is presented. The choice is mainly, but not exclusively governed by two criteria, namely circuit complexity required, and probable production volume and costs. >

Development of a real-time testbed for studying demodulation techniques in a jamming environment

Abstract: A testbed that allows a variety of modulation and demodulation techniques to be implemented in programmable hardware and performance in additive white Gaussian noise (AWGN) and jamming conditions to be measured is described. Field programmable gate array (FPGA) technology is used in the majority of the modulators and demodulators to allow the design to be easily modified to investigate new modulation/demodulation approaches. AWGN hardware performance is compared with theoretical simulations as a check on both implementation loss and simulation validity. A jammer simulator that interfaces with the testbed has also been constructed. Various jammer threats can be introduced on the communications link, and resultant performance can be measured, displayed, and recorded. >

Fast partitioning method for PLA-based architectures

Abstract: Describes a method for automatic partitioning of a given multioutput function into the smallest number of subfunctions such that each subfunction can fit into a fixed size PLA or functional block of a given field programmable gate array (FPGA) chip. The proposed method is fast, efficient and produces almost optimum partitions for the examples which have been tried. The partitioning procedure is in production use as part of an automated design system at Plus Logic. >

Microcontroller Compatible Clock Chip Design Using Field Programmable Gate Array

Abstract: The design and implementation of a microcontroller-compatible real-time clock using a field programmable gate array are presented. The advantage of rapidly prototyping an IC chip design according to user-defined specifications is demonstrated. The chip design is directly interfaced with 10 seven-segment light-emitting diodes for displaying time and calendar information. Translating the clock function to an external peripheral allows the microcontroller to perform other tasks more efficiently. The relatively short cycle time to develop a product from concept to the final chip is described. >

FPGA implementation of the BH8000 wormhole router

Abstract: A Xilinx FPGA was chosen for prototyping a self-timed message routing device. The authors' experience in implementing an asynchronous design on an FPGA, which like most other programmable logic is optimised for synchronous designs, is described. The manual intervention needed at various stages of design implementation is discussed. Debugging and performance issues are looked at and some modifications to the FPGA architecture are suggested. >

Naval Research Laboratory flex processor for radar signal processing

Abstract: This paper describes a programmable radar signal processor architecture developed at the Naval Research Laboratory (NRL). The design incorporates T.I. TMS320C30 programmable digital signal processor devices, Xilinx programmable gate arrays, TRW FFT devices, and a parallel array of Inmos Transputer microprocessors. The architecture is extremely flexible and is applicable to a wide variety of applications.