Showing papers on "Flip-flop published in 1979"

A DC-powered Josephson flip-flop

Abstract: A novel dc-powered flip-flop logic and/or memory element utilizing two Josephson tunneling gates has been designed and tested. Circuit resistances R, critical currents I c , and fanout inductances L are chosen so that the gates operate individually in the latching current-steering mode. However, the gates G1 and G2 are interconnected in such a way that if, say, G1 is at V eq0 and G2 is at V=0, a switching of G2 to V eq0 returns G1 to the V=0 state. The fanout current redistribution, which accompanies this switching event, occurs with a time constant of about L/R. Switching back to the initial state is a symmetric process. Tolerances on circuit parameter values for proper operation are reasonably wide.

Flip-flop circuit

Abstract: Disclosed is a flip-flop circuit capable of high speed and of low power consumption which has a master flip-flop including a logic gate circuit, and a slave flip-flop circuit also including a logic gate circuit, and a means for supplying a preset signal or a clear signal to the logic gate circuit of the slave flip-flop circuit or to an output logic circuit. Specifically, a binary type flip-flop circuit with preset/clear functions suitable for a ring counter and a ripple counter, and assembled by means of integrated circuit technology, is disclosed.

Phase detector for phase locked loops

Abstract: A phase locked loop circuit employing a first edge detector consisting of an exclusive OR gate and flip flop circuit feeding by way of a NAND gate, an up counter and a second edge detector of like kind feeding also by way of a NAND gate into a down counter. Both counters feed into an added which provides a signal to a decoder representing the phase difference between the input phase and the output phase signal. The phase processing system provides positive rapid pull-in over the entire frequency range capability of the VCO, which allows narrow bandwidth loops to track rapid rates of frequency change without loss of lock and with great accuracy.

Frequency and phase comparator

Abstract: First and second triggered D type flip flops activated by input signal pulses and input reference pulses control first and second pulse generating circuits, a set/reset latch, and a clock input of a third edge triggered D type flip flop. A three input exclusive-or gate connected to the first and second edge triggered D type flip flop and to the set/reset latch is active on the data input of the third edge triggered D type flip flop for producing a sign signal of difference frequency. First and second gating circuits and an adding circuit are controlled by the sign signal for producing output pulses of difference frequency. First, second, third, and forth edge triggered pulse generating circuits activated by the first and second edge triggered D type flip flops and the set/reset latch produce pulses, which are distributed by an electronic combinational switch to operate first and second combinational set/reset latches for producing output two phase pulses of difference frequency.

Signal programmable multiple function flip-flop

Abstract: A signal programmable, multiple function flip-flop comprises a clocked, RS master-slave flip-flop with additional logic elements responsive to the signals on a pair of programming inputs to program the operation of the flip-flop as an RS, JK, D or T flip-flop.

Signal transmission circuit using transformer - has bistable flip=flop whose input is coupled to HF oscillator and output to buffer store

Abstract: The circuit is intended for potential separated transmission of digital and analogue signals. It uses for this purpose a transformer whose secondary incorporates a semiconductor rectifier bridge. A bistable flip-flop (1) has its input connected to a high frequency oscillator (2), and its output to a buffer store (3). The output of the buffer store is coupled to the transformer (6) primary. the analog or digital signal to be transmitted is fed to the operating voltage input (4) of the buffer store (3). The circuit is particularly applicable to the control of transistor setting elements in such manner that control signals from a logic circuit are transmitted to a power transistor with its base at floating potential.

Programmable sequence controller with counting function

Abstract: A programmable sequence controller with a counting function comprises an addressable latch circuit including at least one flip flop. A counter is connected to the flip flop such that the content of the counter is changed by one each time the flip flop is set. A setting device is provided for manually setting a count-up value of the counter. A comparator generates a count-up value signal when the counting-up of the counter to the count-up value is detected. A data selector is connected to receive the count-up value signal for supplying a logical value indicative of the status of the comparator. A logic operation circuit is responsive to a test command of a first instruction for testing a logical value of one of a plurality of external input devices and the data selector specified by address data in the first instruction and also responsive to an output command in a second instruction for generating an output command signal based upon the result of the test. The flip flop is set in response to the output command signal generated from the logic operation circuit when the flip flop is designated by the address data.

"D" Flip-flop

Abstract: A "D" flip-flop circuit is disclosed which includes a master latch having data input transistors coupled to the input terminals thereof and data transfer transistors connected to the output thereof. A slave latch is connected to the output terminals of the data transfer transistors. The flip-flop circuit utilizes a resistive feedback network coupled between the emitter terminals of the transistors of the master latch to facilitate increased output voltages and stable predictable operating conditions. The data input transistors are connected as emitter follower circuits for driving the master latch transistors in a common base configuration for maximizing the speed-power product of the circuit.

A high speed I 2 L compatible with high voltage analog devices

Abstract: This paper reports a new approach for realizing a high speed I2L and a high voltage analog circuit simultaneously on a single chip. One significant feature of the new technology is in its high current gain capability for the I2L inverters. Another feature is a precise controllability of the Gummel number for the I2L intrinsic base, utilizing phosphorus and boron double implantations. Typical values of upward current gain for a fan-out of 1 I2L gate and for a fan-out of 10 I2L gate are 45 and 13, respectively. The maximum operating frequency of a divide-by-two I2L circuit is 5.5 MHz and a power-delay product is 0.18 pJ. A high BVCEOof 75 V of the analog transistor is achieved with a toggle frequency of 2.2 MHz for the I2L flip flop circuit.

Integrated circuit device

Abstract: PURPOSE:To execute a self-test for appreciating the reliability by a few additional circuits, by providing 3 terminals for input, output and clock signals for testing, and an input/output control means for testing, in an integrated circuit provided with a data precessing circuit. CONSTITUTION:An integrated circuit device receives a data from an input terminal 11, the date processed by a data processing circuit 16 through a flip flop (FF) 15 is outputted from an output data terminal 12 through FFs 17, 18, and a clock phi is outputted from a terminal 13. In case of executing a test for appreciating the reliability of a data processing device, a test program is executed by the data processing circuit 16, a clock signal phi and a control signal phic are generated, and in case when an output data is sent to an external circuit, the data is set to the FF 17 by the control signal phic from the processing circuit 16, is set to the next FF 18 by the clock phi, is supplied to the external circuit through an output buffer 19, and the external circuit executes a test by synchronizing with the clock phi. A testing data from the external circuit is inputted from the terminal 11.

Telephone set with two repeat dialling memories - allows dialling repetition and number noting and has logic circuit with flip=flop

Abstract: The easy-to-use telephone set retains a telephone number. this allows the user to send it out repeatedly simply pressing one key; there is no need to redial the number. The set has two dialling repeat memories (Wa, Wb) and a logic circuit (4). When one repeat memory contains a call number, which is retained for noting, the logic circuit selects the other repeat memory for dialling repetitions. The logic circuit consists of a flipflop.

Evaluation circuit for semiconductor memory - has flip=flop with two inverter stages, each with four transistors

Abstract: The memory has single transistor storage locations. There is also a flip-flop with two inventor stages and a transversal transistor connecting the invertor outputs for potential equalisation. At least one store bit conductor is connected to a signal output. The flip-flop inventor stages consist of a switching invertor and a control circuit. The inventor comprises a switching transistor (31, 32) and a load transistor (33, 34). The control circuit control input is connected to a flip-flop point (e.g. 45) and an invertor output is connected to the other flip-flop point (e.g. 46). Signal preamplification is carried out by the control circuit in accordance with the storage capacitor (30) charge.

Initial condition set circuit for latch circuit

Abstract: PURPOSE:To make easy circuit integration for the circuit including the latch circiut and to avoid malfunction, by constituting the set circuit with transistors and diodes and resistors without using capacitors. CONSTITUTION:The set circuit is constituted with the DC power supply 1, power supply switch 2, and integrated circuit element 3 consisting of the power supply control circuit 6 controlled with the initial condition set circuit 4, latch circuit 5. With this consitution, the circuit 4 is provided with the transistors Tr1 to Tr6, diodes D1 to D3 and resistors R1 to R3, and power supply is fed to the circuit 5 with Tr3, and power supply is fed to the trigger pulse generation circuit to make the circuit at initial condition from Tr4. Next, the circuit 15 is provided with Tr7 and Tr8, where flip flop operation is made. Further, the circuit 6 consists of Tr9 to Tr11 and resistors R5 and R6, and the supply and interruption of power supply is made with the output of the circuit 5. Thus, the set of initial condition is ensured.

Conversion of timing signals into continuous digital signals - involves shift register and flip=flop whose input state is taken over

Abstract: The timing signals have different pulse and spacing widths, and the circuit has an input for the tining signal and at least one output for continuous digital signals. One of the timing signal (TS) logic states (O) is a first control criterion for activation of a shift register (3) controlled by a shifting pulse generator (6), and its other logic state (1) is a second criterion for the shift register (3) resetting. A D-flip-flop (5) D input is conected to the shift register (3) output (Q2), and the flip-flop is controlled by the edge following the logic state (O), so that the logic state (O, 1) at the flip-flop D input is taken over.

Flip flop circuit

Abstract: PURPOSE:To reduce the occupation area of an FF by decreasing the number of elements even under complicate input conditions, by composing the FF circuit of a C-MOS circuit by employing dynamic circuit technique when inputs meet prescribed requirements CONSTITUTION:Set and reset signals phiS and phiR never have logic 1 simultaneously, and set and reset signals fS and fR never vary while the signals phiS or phiR has logic 1 In C-MOS circuits 20 and 21, a driver-side circuit consists of six n channel MOS transistor TRs TR1-TR6, and a load-side circuit consists of four p channel MOSTRs TR7-TR10 Namely, the TRs TR1, TR2, TR7, and TR8, and TR4, TR5, TR9, and TR10 are connected in series between a power source VDD and a ground terminal Further, the signals phiS, fs, phiR, and fR are supplied to the gates of the TRs TR1 and TR8, the gate of the tRTR2, the gates of the TR TR4 and TR10, and the gate of the TRTR5 Thus, the number of elements is decreased

Power source synchronizing timign set up circuit

Abstract: PURPOSE:To easily obtain the time limit synchronized with alternating power source, by using analogue control element, such as variable resistor etc., as the timing set up device of timer circuit for resistance welding machine and forming asynchronous time limit as the power source through a simple synchronous control circuit. CONSTITUTION:Selection of the analogue switch 2 is determined by each bit output condition of the ring counter 3 composed of the shift register and gate circuit at the timer circuit for resistance welding machine and the value of selected timing set up device 1 is taken in the timing set up circuit 4 composed of IC for timer etc. and then, time limit digital signal is formed. Basing on the above signal, the one shot circuit 5 making clock pulse, is connected with clock input of the counter 3 together with starting pulse. Alternating power source voltage is inputted in the pulse conversion circuit 7 through the transformer 6 and the above signal is made as clock signal. Then, the clock signal is connected with the D type flip flop circuit 8 converting welding current charge time limit signal QW to D input signal and the bit output E is synchronized with QW.

Logical array circuit

Abstract: PURPOSE:To establish the PLA suitable for the programmable timing generator, in which the timing waveform can arbitrarily be controlled depending on the control input and the state of internal flip flop CONSTITUTION:The AND array forms a matrix with 8 input lines a1 to a8 and 8 internal lines O1 to O8, each cross point is provided with a logic element, and P is programmed in conductive state The internal lines O1 to O8 are extended at the input line of the OR array d and they are crossed with the output lines P1 to P8 The counter a in 4-bit advances with the clock input CLK, and the output of each digit having weight of 1,2,4,8 is respectively connected to the input lines a1 to a8 of the AND array C Four sets of J-K flip flop b1 to b4 are connected to the output lines p1 to p8, being controlled with the clock input CLK, and each output Q1 to Q4 are taken as the output of the timing generator

D-type flip=flop with input controlled by pushbutton - has flip=flop input connected through three differentiating circuits to logic switching elements

Abstract: The flip-flop has only two logic switching elements (16, 17). Each of the logic elements is connected to a differentiating circuit (12, 13) whose outputs are connected through a third differentiating circuit (4) to the flip-flop input (1). There are switching elements or diodes (22, 25) which block one or the other differentiating circuits (12, 13) in accordance with the logic state of the flip-flop. Typically NAND gates may be used for the logic elements (16, 17). Alternatively NOR gates or inverter switching networks may be used.

Thyristor ignition control circuit - has three AND=circuits, monostable flip=flop and control counter in logic circuit output stage

Abstract: Thyristors feed signals back to a circuit which comprises a control counter and an output logic unit It is controlled by double and single pulse control telegrams generated in a central control unit The double pulse initiates the ignition phase, and the single pulse initiates individual thyristor monitoring and measurement phases Control telegram pulses are applied to a first AND circuit (G1) and a first monostable flip-flop (M), whose output pulses (m) are applied to a second AND circuit (G2) and to a second input of the first AND circuit (G1) whose output pulses set the counter (Z) to its ignition position (fR) Its last position (N + 1) delivers a pulse to a third AND circuit (G3), and inverted pulse to the second AND circuit (G2) Second AND circuit output pulses (c) are applied to the counter timing input The flip-flop (M) inverted output pulses (m) are applied to a third AND circuit (G3) whose output signals represent signalling back for the ignited thyristor

System for controlling velocity of mobile body

Abstract: PURPOSE:To accomplish a highly pricise controlling of the speed of mobile bodies by a phase locked loop system based on a standard clock from a crystal oscillator CONSTITUTION:A signal from a mobile body position detectors 13A and 13B are inputted to a flip flop (FF) 18 through waveform formation circuits 16a and 16b and differential circuits 17a and 17b The output signal of the flip flop 18 is applied to an AND circuit 19 together with a standard clock pulse from a crystal oscillator 20 The output signal of the circuit 19 is fed to a subtraction circuit 23 through a counter 21 and a latch circuit 22 An output signal 18d from the invertional output terminal of the flip flop 18 passes through a delay circuit 24 and is separated into a signal for resetting the counter 21 through a delay circuit 25 and a differential circuit 26 and a signal to be inputted to the load terminal of the circuit 22 through a differentiation circuit 27 The output of the circuit 29 provides a drive signal of a desired speed to mobile bodies

J-K flip-flop for C-MOS integrated circuits

Abstract: A J-K flip-flop circuit for integrated C-MOS family is described. The new device employs a simple excitation circuitry which improves the speed—power product. Results of a comparison with the conventional flip-flop are also given.

Sample and hold circuit for binary signals - has flip=flop comprising two pairs of complementary FETS

Abstract: The sample and hold circuit stores destination addresses in data systems and its output is connected to the system's address decoder. The circuit contains a flip flop comprising two pairs of complementary transistors. The transistors in the first pair have equal capacitances. A drive circuit is connected to the input and has a drive path and a compensation path for the capacitance of the drive path. The sample is applied to the source of the transistors in the first pair. A device detects the final state of the flip flop and inhibits the drive circuit's paths.