Showing papers on "Gate count published in 1990"

ATPG for ultra-large structured designs

Abstract: A ATPG (automatic test pattern generation) system that can efficiently create a high-coverage test for extremely large scan designs is described This system is formed by optimally combining a fast fault simulator with a powerful test generator For the ISCAS85 and ISCAS89 circuits, this ATPG system created a test for all testable faults and identified all redundant faults without a single aborted fault This represents the first time this has been achieved for the ISCAS89 designs, and the performance of this ATPG system is significantly better than published results Performing ATPG for the largest ISCAS89 designs, which contained about 25000 gates, required only 3 min of CPU time on an Apollo DN3550 workstation The data collected for the ISCAS designs showed that the ATPG CPU time increased linearly with gate count This strongly suggests that ATPG can be efficiently performed for circuits of 100000 and even one million gates >

The minimal test set for sorting networks and the use of sorting networks in self-testing checkers for unordered codes

Abstract: It is shown that an n-input sorting network (SN) can be used to implement all n-variable symmetric threshold functions, using the least amount of hardware. A procedure of generating the minimal test set for K.E. Batcher's SNs is presented. An upper bound is determined for the number of tests required to detect all stuck-at faults in an n-input SN; it is fewer than in similar designs used to date. Finally, it is shown that the SNs can be used to realize easily testable self-testing checkers (STCs) for m-out-of-2m codes and all J.M. Berger codes. The new STCs for m/2m codes (m>3) have the lowest gate count and require the fewest number of tests. Upper bounds are also found for the number of tests required by the new STCs for Berger codes with I information bits. For I>or=14 they require fewer gates than similar designs known to date. >

Analysis of propagation delays in high-speed VLSI circuits using a distributed line model

Abstract: A scattering parameter-based homogeneous distributed-line model with arbitrary initial and boundary conditions is proposed and its implementation in a general-purpose circuit simulator supporting user functions is described. Using a GaAs 0.5- mu m MESFET technology, the chip delays in very high-speed VLSI circuits are calculated. The performance requirements of transistors for high-density integration and for long-distance interconnection drivers are discussed with respect to properties of lossy and lossless interconnection lines. The evaluation of chip delays shows that sub-100-ps VLSI circuits (gate count beyond 10/sup 5/) should involve: (1) complementary logic gates using transistors with transconductance of 1-2.5 S/mm; and (2) high T/sub c/ superconducting long-distance interconnection lines driven by bipolar circuits with transconductance of 2.5 S/mm, unless such long lines can be overcome by new chip architectures. >

A new arbitration circuit for synchronous multiple bus multiprocessor systems

Abstract: A novel design for an M-user B-server arbiter for a multiple bus system is presented. The arbitration circuit maintains fairness when it is used in a low-order interleaved memory system. The arbiter is also fair for a general-purpose multiprocessor system where the memory modules are uniformly accessed by the processors. The arbitration time grows at a rate O(log/sub 2/ M), where M is the number of memory modules in a system. When a system has more than four memory modules, both the gate count and delay of the present design are less than those of previous designs. >

Theory and applications of free-space digital optical computing

Abstract: A methodology for designing digital circuits is described for systems using free-space optics as an interconnection medium. Free-space optics offers the potential for a connectivity advantage over guided-wave optical interconnects and electronic interconnects, but new design techniques are needed to exploit that potential. Connections are made among arrays of optically nonlinear logic gates with regular interconnection patterns such as perfect shuffles, banyans, and crossovers. Design methods are based on symbolic substitution which is a form of cellular automata suited for array scale operations. Methods are introduced in the form of simple automata that are relatively easy to implement with free-space optics. More complex techniques are presented that utilize regular interconnects among logic gates and yield digital circuits nearly as efficient as conventional design techniques allow utilizing arbitrary interconnects, but that are suited for a simpler free-space architecture. The cost of using regular free-space interconnects throughout a digital optical computer is greater than would be realized with a completely arbitrary interconnect in terms of gate count and circuit depth. This increased cost is small when compared with limitations posed by electronic interconnects and system costs introduced by optical implementations of arbitrary interconnects provided by means such as fibers or holograms. It is concluded that regular-free space interconnection is a preferred medium for interconnection in digital optical computing.

Experimental evaluation of concurrent fault simulation algorithms on scalable, hierarchically defined test cases

Abstract: The authors have implemented three concurrent fault simulation algorithms and applied them to several circuit families. The algorithms are concurrent fault simulation (CFS), hierarchical concurrent fault simulation (HCFS), and a modification of HCFS called bundled hierarchical fault simulation (BHCFS). In BHCFS, a structure is imposed upon the simulation error lists, which can produce a significant reduction in simulation run time. A prototype of each algorithm has been applied to circuit families of varying size to generate actual run-time data. The circuits are scalable (to some granularity) in gate count. This property allows the simulator run-time data to be presented as a function of circuit size without the effects of varying circuit topology. It is shown experimentally that the run time for BHCFS grows nearly linearly with acyclic circuit gate count but approaches a higher order in tightly connected sequential circuits. It is also confirmed that HCFS exhibits near N log N behaviour in circuits which have reasonably well-balanced design hierarchy. In absolute run time, both hierarchical algorithms outperformed flat CFS at the gate level in all examples except one, which had an extremely unbalanced hierarchy. Overall, BHCFS shows the best performance in acyclic circuits and good performance in loosely coupled sequential circuits. >

Synthesis of optimized ASIC DSP systems

Abstract: GAD, a synthesis tool for ASIC (application-specific integrated circuits) DSP (digital signal processing) systems, is presented. Given the signal flowgraph, the required system throughput, and a number of other optimization parameters, GAD produces the gate-level implementation of the system, which is optimized according to the total gate count of the realization. The types of DSP systems targeted are arithmetic datapaths without conditional branches and simple in control. GAD tries to maximize resource sharing during scheduling to reduce cost. A number of cost-saving design techniques for DSP systems have also been encapsulated as independent optimization procedures. GAD is linked to the design of actual silicon through module generators that provide information on the delays, gate counts, and netlists of the modules. Operator types are still limited in GAD. Handling of operations such as round, truncate, and shift are also very much needed. Additional flexibilities are needed for including controls in the system. >

GaAs VLSI technology and circuit elements for DSP

Abstract: Recent progress in digital GaAs circuit performance and complexity is presented to demonstrate the current capabilities of GaAs components. High density GaAs process technology and circuit design techniques are described and critical issues for achieving favorable complexity speed power and cost tradeoffs are reviewed. Some DSP building blocks are described to provide examples of what types of DSP systems could be implemented with present GaAs technology. DIGITAL GaAs CIRCUIT CAPABILITIES In the past few years the capabilities of digital GaAs circuits have dramatically increased to the VLSI level. Major gains in circuit complexity and power-delay products have been achieved by the use of silicon-like process technologies and simple circuit topologies. The very high speed and low power consumption of digital GaAs VLSI circuits have made GaAs a desirable alternative to high performance silicon in hardware intensive high speed system applications. An example of the performance and integration complexity available with GaAs VLSI circuits is the 64x64 crosspoint switch shown in figure 1. This switch which is the most complex GaAs circuit currently available is designed on a 30 gate GaAs gate array. It operates at 200 MHz and dissipates only 8 watts of power. The reasons for increasing the level of integration of GaAs circuits are similar to the reasons for the continued increase of silicon circuit complexity. The market factors driving GaAs VLSI are system design methodology system cost power and reliability. System designers are hesitant or unwilling to go backwards to previous design techniques and lower levels of integration. A more highly integrated system in a lower performance technology can often approach the performance of a system in a higher performance technology at a lower level of integration. Higher levels of integration also lower the system component count which reduces the system cost size and power consumption while improving the system reliability. For large gate count circuits the power per gate must be minimized to prevent reliability and cooling problems. The technical factors which favor increasing GaAs circuit complexity are primarily related to reducing the speed and power penalties incurred when crossing chip boundaries. Because the internal GaAs chip logic levels are not compatible with standard silicon I/O levels input receivers and output drivers are needed to convert levels. These I/O circuits add significant delay to logic paths consume large amounts of power and use an appreciable portion of the die area. The effects of these I/O penalties can be reduced by increasing the ratio of core logic to I/O on a chip. DSP operations which have a large number of logic stages between the input and the output are ideal candidates to take advantage of the performance of GaAs digital circuits. Figure 2 is a schematic representation of the I/O penalties encountered when converting from ECL levels to GaAs