Showing papers on "Ground bounce published in 2020"
TL;DR: An efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise is presented.
Abstract: This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.
30 citations
TL;DR: In this paper, a mushroom-like EBG and power bus structure were derived using the modified nodal analysis (MNA) method, which enhanced the suppression of simultaneous switching noise coupling (≤−40 dB) within the range of 260 MHz to 10 GHz.
Abstract: Adding mushroom-like electromagnetic band-gap (EBG) structures to split power planes can produce wideband suppression of ground bounce noise in high-speed printed circuit boards. Practical equations are used to estimate the stop-band performance of EBG structures within parallel power planes. In this article, a mushroom-like EBG and power-bus structure are derived using the modified nodal analysis (MNA) method. Equations calculated using the MNA method are easily programmable. The partial EBG structures developed in this article can suppress noise from electromagnetic (EM) interference within parallel plates in the power bus. Several examples below show that similar results can be obtained in measurements, in EM simulations software, and in derived equations. The proposed structure enhanced the suppression of simultaneous switching noise coupling (≤−40 dB) within the range of 260 MHz to 10 GHz.
7 citations
Patent•
10 Jan 2020
TL;DR: In this paper, the authors proposed an output driving circuit capable of resisting ground bounce noise, and belongs to the field of semiconductor integrated circuits, where a certain time delay is introduced in the switching conversion process of an output-driving PMOS transistor and an NMOS transistor by adding a logic circuit to avoid simultaneous conduction of the PMOS and the NMOS transistors.
Abstract: The invention relates to an output driving circuit capable of resisting ground bounce noise, and belongs to the field of semiconductor integrated circuits. According to the output driving circuit, certain time delay is introduced in the switching conversion process of an output driving PMOS transistor and an NMOS transistor by adding a logic circuit to avoid simultaneous conduction of the PMOS transistor and the NMOS transistor, and different driving capacities of the circuit in the static state and in the switching process are realized by making the driving transistors with different width-to-length ratios switched on successively. The output driving circuit can reduce the ground bounce noise, and has high driving capacity.