Efficient Jitter Analysis for a Chain of CMOS Inverters

Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator

Abstract: This paper presents the timing error and power supply induced jitter (PSIJ) analyses of an inverter based high-speed comparator, including the design of common-mode body biasing feedback circuitry. Both the main circuit and the supporting circuitry have been designed and implemented in a standard 28 nm CMOS technology with power supply of 0.9 V. The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method. The mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE).

An IBIS-like Modelling for Power/Ground Noise Induced Jitter under Simultaneous Switching Outputs (SSO)

Abstract: This paper presents an assessment of jitter induced by power and ground (P/G) voltage variations. The assessment is based on an extended input/output buffer information specification (IBIS)-like model for capturing the effect of P/G signal variations under simultaneous switching output (SSO) buffers. The requirements of nonlinear modeling for the accurate prediction is explained and illustrated. The implemented large signal equivalent-circuit model is validated under different test conditions having different P/G voltage variations for predicting the output signal distortions. The associated jitter analysis by predicting the eye diagram under the noise conditions is performed. The maximum values of the prediction error for the peak to peak values of eye jitter and eye height are 7.06% and 2.59%, respectively.

A 6-Bit, 29.56 fJ/Conv-Step, Voltage Scalable Flash-SAR Hybrid ADC in 28 nm CMOS

Abstract: This paper presents the design of a 6-bit scalable hybrid flash SAR (successive approximation register) analog-to-digital converter (ADC). The ADC has a scalable architecture because of the usage of an inverter based comparator. The conversion time is reduced by adopting a 3-bit/cycle approach. A segmented split-capacitor charge redistribution digital-to-analog converter (CDAC) is used to reduce the DAC settling time and the design area. The ADC is implemented in a 28 nm CMOS technology with the scalable V DD from 0.5 V to 1 V. The ADC operates from 10 MHz to 1.1 GHz for a V DD of 0.5 V to 1 V respectively. The design shows 47.7 fJ/conv-step and 29.56 fJ/conv-step for V DD of 0.9 V and 0.6 V respectively.

Analysing the Impact of Various Deterministic Noise Sources on Jitter in a CMOS Inverter

Abstract: This paper presents an analysis of jitter due to various deterministic noise sources in a CMOS inverter. The results obtained from the semi-analytical jitter estimation approach presented in the paper are compared with the results obtained from full SPICE based simulations. For the estimation of jitter, EMPSIJ method [1] is used in the paper. The paper also discusses the sensitivity of various noise paths on jitter.

A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers

Abstract: This paper presents an efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources. Generalised semi-analytical relations between noise and PSIJ are developed using Thomas algorithm. The proposed analysis can be used for both cases of same size of inverters as well as tapered buffers, and also for considering the effect of on-chip and off-chip interconnects. The validity and the efficiency of the proposed modeling is demonstrated for various applications of chain of inverters such as buffers in clock distribution, delay locked loops and I/Os, etc.

Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas

Abstract: An alpha -power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced. The model is an extension of Shockley's square-law MOS model in the saturation region. Since the model is simple, it can be used to handle MOSFET circuits analytically and can predict the circuit behavior in the submicrometer region. Using the model, closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived. The delay expression includes input waveform slope effects and parasitic drain/source resistance effects and can be used in simulation and/or optimization CAD tools. It is found that the CMOS inverter delay becomes less sensitive to the input waveform slope and that short-circuit dissipation increases as the carrier velocity saturation effect in short-channel MOSFETs gets more severe. >

Signal and Power Integrity - Simplified

Abstract: The #1 Practical Guide to Signal Integrity DesignNow Updated with Extensive New Coverage!This book brings together up-to-the-minute techniques for finding, fixing, and avoiding signal integrity problems in your design. Drawing on his work teaching more than five thousand engineers, world-class signal and power integrity expert Eric Bogatin systematically reviews the root causes of all six families of signal integrity problems and shows how to design them out early in the design cycle. This editions extensive new content includes a brand-new chapter on S-parameters in signal integrity applications, and another on power integrity and power distribution network designtopics at the forefront of contemporary electronics design.Coverage includesA fully up-to-date introduction to signal integrity and physical designHow design and technology selection can make or break the performance of the power distribution networkExploration of key concepts, such as plane impedance, spreading inductance, decoupling capacitors, and capacitor loop inductancePractical techniques for analyzing resistance, capacitance, inductance, and impedanceSolving signal integrity problems via rules of thumb, analytic approximation, numerical simulation, and measurementUnderstanding how interconnect physical design impacts signal integrityManaging differential pairs and lossesHarnessing the full power of S-parameters in high-speed serial link applicationsEnsuring power integrity throughout the entire power distribution pathRealistic design guidelines for improving signal integrity, and much moreUnlike books that concentrate on theoretical derivation and mathematical rigor, this book emphasizes intuitive understanding, practical tools, and engineering discipline. Designed for electronics industry professionals from beginners to experts it will be an invaluable resource for getting signal integrity designs right the first time, every time.

Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions

Abstract: This paper reviews recent progress and future directions of signal integrity design for high-speed digital circuits, focusing on four areas: signal propagation on transmission lines, discontinuity modeling and characterization, measurement techniques, and link-path design and analysis.

Jitter, Noise, and Signal Integrity at High-Speed

Abstract: State-of-the-art JNB and SI Problem-Solving: Theory, Analysis, Methods, and ApplicationsJitter, noise, and bit error (JNB) and signal integrity (SI) have become today's greatest challenges in high-speed digital design. Now, there's a comprehensive and up-to-date guide to overcoming these challenges, direct from Dr. Mike Peng Li, cochair of the PCI Express jitter standard committee.One of the field's most respected experts, Li has brought together the latest theory, analysis, methods, and practical applications, demonstrating how to solve difficult JNB and SI problems in both link components and complete systems. Li introduces the fundamental terminology, definitions, and concepts associated with JNB and SI, as well as their sources and root causes. He guides readers from basic math, statistics, circuit and system models all the way through final applications. Emphasizing clock and serial data communications applications, he covers JNB and SI simulation, modeling, diagnostics, debugging, compliance testing, and much more.Coverage includes? JNB component classification, interrelationships, measurement references, and transfer functions Statistical techniques and signal processing theory for quantitatively understanding and modeling JNB and related components Jitter, noise, and BER: physical/mathematical foundations and statistical signal processing views Jitter separation methods in statistical distribution, time, and frequency domains Clock jitter in detail: phase, period, and cycle-to-cycle jitter, and key interrelationships among them PLL jitter in clock generation and clock recovery Jitter, noise, and SI mechanisms in high-speed link systems Quantitative modeling and analysis for jitter, noise, and SI Testing requirements and methods for links and systems Emerging trends in high-speed JNB and SI As data rates continue to accelerate, engineers encounter increasingly complex JNB and SI problems. In Jitter, Noise, and Signal Integrity at High-Speed, Dr. Li provides powerful new tools for solving these problemsi??quickly, efficiently, and reliably.Preface xvAcknowledgements xxiAbout the Author xxiiiChapter 1: Introduction 1Chapter 2: Statistical Signal and Linear Theory for Jitter, Noise, and Signal Integrity 27Chapter 3: Source, Mechanism, and Math Model for Jitter and Noise 75Chapter 4: Jitter, Noise, BER (JNB), and Interrelationships 109Chapter 5: Jitter and Noise Separation and Analysis in Statistical Domain 131Chapter 6: Jitter and Noise Separation and Analysis in the Time and Frequency Domains 163Chapter 7: Clock Jitter 185Chapter 8: PLL Jitter and Transfer Function Analysis 209Chapter 9: Jitter and Signal Integrity Mechanisms for High-Speed Links 253Chapter 10: Modeling and Analysis for Jitter and Signaling Integrity for High-Speed Links 281Chapter 11: Testing and Analysis for Jitter and Signaling Integrity for High-Speed Links 309Chapter 12: Book Summary and Future Challenges 345Index 353

Buffer delay change in the presence of power and ground noise

Abstract: Variations of power and ground levels affect very large scale integration circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise-on-signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply-level-induced jitter characteristics. The expressions can be used in any existing circuit performance optimization design flow or can be combined into any delay calculations as a correction factor.