Journal ArticleDOI
Efficient Jitter Analysis for a Chain of CMOS Inverters
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TLDR
An efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise is presented.Abstract:
This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the presence of multiple noise sources, including the power supply noise, input data noise, and the ground bounce noise. For this purpose, necessary noise transfer functions are derived and the recently developed EMPSIJ method is advanced to handle cascaded CMOS inverter stages. Results from the proposed method are compared with the results from a conventional EDA simulator, which demonstrate a significant speed-up using the proposed method for a comparable accuracy.read more
Citations
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Journal ArticleDOI
Device Parameter-Based Analytical Modeling of Power Supply Induced Jitter in CMOS Inverters
TL;DR: In this article, an analytical approach to determine jitter for a CMOS inverter in the presence of power supply noise (PSN) is presented, where the deviation in the transition edge of the output signal from its ideal timing is modeled accurately for each transition.
Proceedings ArticleDOI
An IBIS-like Modelling for Power/Ground Noise Induced Jitter under Simultaneous Switching Outputs (SSO)
TL;DR: In this paper, an assessment of jitter induced by power and ground (P/G) voltage variations is presented based on an extended input/output buffer information specification (IBIS)-like model for capturing the effect of P/G signal variations under simultaneous switching output (SSO) buffers.
Proceedings ArticleDOI
Analysis of Timing Error Due to Supply and Substrate Noise in an Inverter Based High-Speed Comparator
Vijender Kumar Sharma,B. Dinesh Kumar,Muhammed Suhail Illikkal,Jai Narayan Tripathi,Navneet Gupta,Hitesh Shrimali +5 more
TL;DR: The closed-form transfer function of the comparator including biasing circuitry, used in PSIJ analysis, is derived using symbolic admittance method and the mathematical model shows an agreement with the simulation and exhibits 7.4% of mean percentage error (MPE).
Proceedings ArticleDOI
Analysing the Impact of Various Deterministic Noise Sources on Jitter in a CMOS Inverter
TL;DR: The results obtained from the semi-analytical jitter estimation approach presented in the paper are compared with the results obtained with full SPICE based simulations.
Journal ArticleDOI
A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers
TL;DR: An efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources is presented.
References
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Journal ArticleDOI
Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
Takayasu Sakurai,A.R. Newton +1 more
TL;DR: In this paper, an alpha-power-law MOS model that includes the carrier velocity saturation effect, which becomes prominent in short-channel MOSFETs, is introduced and closed-form expressions for the delay, short-circuit power, and transition voltage of CMOS inverters are derived.
Book
Signal and Power Integrity - Simplified
TL;DR: This book brings together up-to-the-minute techniques for finding, fixing, and avoiding signal integrity problems in your design and will be an invaluable resource for getting signal integrity designs right the first time, every time.
Journal ArticleDOI
Signal Integrity Design for High-Speed Digital Circuits: Progress and Directions
TL;DR: This paper reviews recent progress and future directions of signal integrity design for high-speed digital circuits, focusing on four areas: signal propagation on transmission lines, discontinuity modeling and characterization, measurement techniques, and link-path design and analysis.
Book
Jitter, Noise, and Signal Integrity at High-Speed
TL;DR: The fundamental terminology, definitions, and concepts associated with JNB and SI, as well as their sources and root causes are introduced, and Dr. Li provides powerful new tools for solving these problems quickly, efficiently, and reliably.
Journal ArticleDOI
Buffer delay change in the presence of power and ground noise
TL;DR: An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply-level-induced jitter characteristics, consistent with short-channel MOSFET behavior, including carrier velocity saturation effects.