Showing papers on "Integral nonlinearity published in 2023"

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

Abstract: The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/−0.6 LSB, and integral nonlinearity (INL) of +1.2/−1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links

Abstract: This article details the design and measurement of a digital-to-analog converter (DAC)-based source-series terminated (SST) transmitter (TX) for wireline applications in 4-nm FinFET CMOS technology. The DAC achieves 8-bit resolution and high analog output bandwidth by using a segmented architecture along with a single-ended LSB. Strength adjustment of the lower four DAC LSBs relative to the upper four DAC MSBs is accomplished with a hybrid analog/digital tuning approach, which overcomes minimum device-size limitations that can limit the effectiveness of pure digital tuning for SST drivers. The resulting DAC design achieves well-matched MSB/LSB segments with −0.63/0.67 LSB integral nonlinearity (INL) and −0.16/0.43 LSB differential nonlinearity (DNL). Time-domain modulation of 216-Gb/s PAM8 and frequency-domain modulation of 212-Gb/s orthogonal frequency-division multiplexing (OFDM) are reported, demonstrating the capability of CMOS DACs to support frequency-domain modulation for wireline applications. The TX consumes 288 mW from a 0.95-V power supply.

Spin-Orbit Torque Flash Analog-to-Digital Converter

Abstract: Although Analog-to-digital converters (ADCs) are critical components in mixed-signal integrated circuits (IC), their performance has not been improved significantly over the last decade. To achieve a radical improvement (compact, low power and reliable ADCs), spintronics can be considered as a proper candidate due to its compatibility with CMOS and wide applications in storage, neuromorphic computing, and so on. In this paper, a proof-of-concept of a 3-bit spin-CMOS Flash ADC using in-plane-anisotropy magnetic tunnel junctions (i-MTJs) with spin-orbit torque (SOT) switching mechanism is designed, fabricated and characterized. The proposed ADC replaces the current mirrors and power-hungry comparators in the conventional Flash ADC with seven parallel i-MTJs with different heavy metal (HM) widths. Monte-Carlo simulations based on the experimental measurements show the process variations/mismatch limits the accuracy of the proposed ADC to 2 bits. Moreover, the maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.739 LSB (least significant bit) and 0.7319 LSB, respectively.

Automated INL and DNL Testing System as a Didactic Laboratory Application

Abstract: Measurement systems are based on analog to digital converters because they offer easy data processing, storage and transmission. Since the majority of the measuring instruments includes ADCs, it is important for students studying Electric and electronic measurements to learn about the parameters of an ADC. INL (Integral nonlinearity) and DNL (Differential nonlinearity) are two of the most important parameters that characterize an ADC, but the process is also time consuming. The present paper presents an automated test system for didactic laboratory. The DUT is a NI DAQ card, the reference instrument is a high accuracy voltage source and the associated software is developed in LabVIEW. The tested parameters are calculated automatically during the process and are displayed on graphs as well as stored in a data file. As conclusions the results are analyzed for comparing the digital code data and the calibrated voltage data.

Design of 8-Bit Hybrid Current Steering Digital to Analog Converter in a Standard 65nm CMOS Technology

Abstract: A digital-to-analog converter (DAC) in electronics is a device that transforms digital signals into analog signals. There are various DAC architectures, and DAC's usefulness for a given application is determined by factors like resolution, INL, DNL, power consumption, maximum sampling frequency, and others. Because digital-to-analog conversion may damage a signal, a DAC with negligible faults for the application should be used. The current-steered digital-to-analog converter is well suited for high-speed applications because no buffers are needed for current steering architectures and the output is the total current drawn from the supply. In this paper, an 8-bit hybrid current steering digital-to-analog converter is proposed. Four cascode current sources with different weights are used in this architecture. The UMC 65nm CMOS technology was used to design the digital-to-analog converter. The INL and DNL were +0.19/-0.15 LSB and +0.28/-0.11 LSB respectively. The DAC uses roughly 3.25 mW at a supply voltage of 1.2V and a sample rate of 100 MHz. 12.751 mV was the output voltage at full scale. In comparison to earlier reports, the power, INL, DNL, and chip area used by the digital-to-analog converter in this architecture were significantly lower. It is appropriate for use in portable devices.

High-Linearity and High-Speed ROIC of Ultra-Large Array Infrared Detectors Based on Adaptive Compensation and Enhancement

Abstract: In order to solve the problem of limited linearity and frame rate in the large array infrared (IR) readout integrated circuit (ROIC), a high-linearity and high-speed readout method based on adaptive offset compensation and alternating current (AC) enhancement is proposed in this paper. The efficient correlated double sampling (CDS) method in pixels is used to optimize the noise characteristics of the ROIC and output CDS voltage to the column bus. An AC enhancement method is proposed to quickly establish the column bus signal, and an adaptive offset compensation method is used at the column bus terminal to eliminate the nonlinearity caused by the pixel source follower (SF). Based on the 55 nm process, the proposed method is comprehensively verified in an 8192 × 8192 IR ROIC. The results show that, compared with the traditional readout circuit, the output swing is increased from 2 V to 3.3 V, and the full well capacity is increased from 4.3 Me- to 6 Me-. The row time of the ROIC is reduced from 20 µs to 2 µs, and the linearity is improved from 96.9% to 99.98%. The overall power consumption of the chip is 1.6 W, and the single-column power consumption of the readout optimization circuit is 33 μW in the accelerated readout mode and 16.5 μW in the nonlinear correction mode.

A new test method for digital-to-analog converter

Abstract: A new BIST (Built-In Self-Test) method to test static parameters of a DAC (Digital to Analog Converter) is proposed in this paper. The BIST method employs a ramp generator and two voltage references to test static parameters of a DAC: offset error, gain error, INL (Integral Non-Linearity) and DNL (Differential Non-Linearity). The optimization of calculating static parameters and the components sharing can reduce the BIST circuitry. The simulation result shows that the method is able to detect the static errors with the simple BIST structure.

A Low-Cost FPGA-Based Coarse-Fine Counting Time-to-Digital Converter With External High-Precision Reference Clock

Abstract: A new coarse-fine counter time-to-digital converter (TDC) architecture and its implementation techniques for high-precision time-interval measurement are presented. Multi-coarse counters and one fine counter are combined in our TDC architecture. The calibration circuit employs a START and STOP calibration signal generator and a gain calibration circuit. Arbitrarily small time intervals can be measured by distributing the START and STOP signals on different channels. In the implementation process, the high-precision external clock produced by a Silicon Si5338 EVB board and the on-chip high-precision clock are combined to calibrate the TDC output data in real-time. The TDC is implemented on a specially designed FPGA board with a low-cost Xilinx Artix-7 35T FPGA. The measured least significant bit (LSB) is 17.9 ps and the calculated peak-to-peak differential nonlinearity (DNL) and integral nonlinearity (INL) values are 1.006 and 0.920 LSB. The root-mean-square (RMS) resolution is lower than 20 ps in continuous measurement.

Dose dependence of the spectral characteristics of sigma-delta analog-to-digital converters

Abstract: This paper presents the results of the study of sigma-delta analog-to-digital converters` main spectral parameters` dependence on the total ionizing dose (TID). Within the framework of this study the main parameters of analog-to-digital converters (ADC) (dynamic, static and electrical) were controlled. The main dynamic characteristics of sigma-delta ADC are signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), signal-to-noise and distortion ratio (SINAD) and total harmonic distortion (THD). Those have been determined from the spectrum of digitized sine signal using the fast Fourier transform (FFT). Static parameters (integrated nonlinearity (INL), offset and gain errors) were determined using a straight line that linearizes the transfer function, according to the method which is described in the IEEE Standard for Terminology and Test Methods for Analog-to-Digital Converters. National Instruments modular measuring equipment was used for testing ADC`s parameters. Comparative data on the dose dependence of static and dynamic parameters of two sigma-delta ADC and one sigma-delta modulator are obtained. Based on the results, it was concluded that the most sensitive parameters of sigma-delta ADC to TID are its dynamic parameters. Therefore, when assessing the sigma-delta ADC`s radiation hardness, the spectral characteristics of absorbed dose should be kept under control.

Homogeneity Enforced Calibration for Pipelined ADCs Including Nonlinear Stage Amplifiers

Abstract: High-speed pipelined analog-to-digital converters (ADCs) are central components in many signal processing systems. Besides a high sampling rate, linearity is a key performance criterion for ADCs. The ADC’s linearity can be drastically increased with calibration techniques, which are heavily investigated. On this matter, the homogeneity enforced calibration (HEC) approach was recently introduced, covering gain and digital-to-analog converter (DAC) mismatches of a pipelined ADC. The HEC approach enables short calibration times, and high calibration performance without the need for a precisely known test signal. In this work, we improve the HEC approach such that nonlinear stage amplifiers are calibrated besides gain and DAC mismatches. The calibration performance of the improved HEC approach is verified with behavioral simulations and shows a high spurious-free dynamic range (SFDR) improvement of 42.7dB and a low remaining integral nonlinearity (INL).

A 128-channel time-to-digital converter based on the 24-phase shift-clock sampling method for RPC

Abstract: Abstract The Resistive Plate Chamber (RPC) are widely used in high energy physics (HEP) experiments. In recent years, new designs and application scenarios of RPCs abound, and an advanced time-to-digital converter (TDC) system is in demand. The TDC implemented in the field-programmable gate array (FPGA) is widely used in HEP experiments with changeable conditions as a flexible time measurement method. This article presents a multi-phase shift-clock sampling FPGA-based TDC with 128 channels. The TDC module is implemented in a Xilinx Kintex-7 FPGA. The sampling clock period (2.22 ns) is subdivided into 24 phases to achieve finer time resolution. The TDC performance measurements show that the root-mean-square (RMS) time resolution of the TDC module in the time interval measurement is 45.3 ∼ 57.7 ps, and the integral nonlinearity (INL) is smaller than 0.2368 least significant bit (LSB). In addition, some target designs are made to adapt to the application scenarios. This article also shows measurement results acquired from an RPC by this TDC. This TDC was used to measure the RPC efficiency plateau and the TOT of the RPC readout signal.

Development and Efficiency Analysis of a Switching Scheme for INL Reduction in Unary DACs

Abstract: This brief is devoted to development of a switching scheme for unary digital-to-analog converters (DACs). Switching schemes are one of possible solutions to compensate the influence of the component value deviations appearing during integrated circuit production. Previously known deterministic switching schemes have some weak points, which limit the compensation with resolution growth. In order to overcome such drawbacks, this work adapts the properties revealed and employed in switching schemes, where each element is split into several parts. Based on these properties, the novel Hierarchical Chessboard Flip (HCF) switching scheme is proposed. Simulation demonstrated that HCF reduces the integral nonlinearity (INL) better than previously known solutions while being scalable to any even bit number in DAC array. Adoption to odd resolutions is also possible. Additionally, an extension of the commonly-used simulation approach is introduced. Obtaining a dependence of INL reduction on the rotation angle of error profile may reveal a weakness of some switching scheme in spite of competitive average values.

A 10-bit 20 Channel LCD Column Driver using Compact DAC

Abstract: A 20-channel liquid crystal display (LCD) driver architecture is implemented with 0.18μm CMOS technology. This work presents a novel design of 10-bit compact and high-resolution two-stage DAC to improve the linearity and uniformity of each channel performance. A complete column driver, including a compact DAC, low power buffer, global R-string and multiplexing circuit design, is implemented, and the layout of this 20-channel, 10-bit LCD driver is generated using 0.18μm CMOS technology. All the circuit blocks of the proposed LCD column driver were simulated using the EDA tool HSPICE and layout generation by Laker. This work also realizes a high-performance class AB operational amplifier with a gain of 140dB for the proposed LCD driver. The 10-bit compact LCD driver has a 1.4 mV LSB and an output voltage of 1.7 V is achieved for the input range of 0.25–1.7V. The compact DAC voltage selector with decoder in this design uses fewer switches in comparison to conventional tree-type RDAC, occupying a smaller chip area with fast response. The proposed design is sufficiently robust for high-color depth and resolution LCD driver applications. The experimental results exhibit maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.065 LSB and −0.12 LSB, respectively. The one channel area is 951.69μm×17.8μm and the settling time is 5.65μs for the 20kΩ and 20pF driving load.

A 12-bit Low-input Capacitance SAR ADC with a Rail-to-Rail Comparator

Abstract: The input capacitance of the SAR ADC is considered as a drawback in many applications. In this paper, a 12-bit low-power SAR ADC with low-input capacitance SAR based on separated DAC and sample-and-hold blocks (SB) structure is proposed. The SB structure suffers from variation of the input common-mode voltage of the comparator causing nonlinear input-referred offset and kickback noise. Here, a closed loop low-power rail-to-rail offset cancellation technique for the comparator based on the body voltage tuning is proposed. In order to stabilize the closed loop structure, the open loop gain is controlled by adapting the gain of the preamplifier. Using this structure, the rail-to-rail offset is kept lower than 110 μV and the overall power of the comparator is 1 pJ/Conv. Complementary-clocked dynamic branches are exploited at the input the comparator to decrease the common-mode dependent kickback noise error to less than 1 LSB. The bootstrapped switch’s controlling signal is also modified to achieve less than 1 LSB error and 18.9% less power consumption. The proposed ADC is designed in standard 180 nm CMOS technology with a 1.8 V supply voltage and shrinking the input capacitance to 2 pF, which leads to 41 nW power consumption in the input voltage supply. Electrical simulations including PVT, Monte-Carlo, and post-layout parasitic extraction were run to ensure the effectiveness of the approach. The ADC features an ENOB of 11.1-bit and the sampling rate of 1 MHz with a power consumption of 117.9 μW including the input power supply which are competitive with the state-of-the-art, and demonstrate the virtue of the proposed approach.

A 2.5 GS/s, 7-bit time-interleaved SAR ADC with real-time data output

Abstract: This letter presents the design and measurement results of a 2.5 GS/s 7-bit successive approximation register (SAR) analog-to-digital converter (ADC) with real-time data output via the JESD204B protocol using two lanes at 12.5 Gb/s each. The ADC is implemented in a 22-nm fully-depleted silicon-on-insulator (FDSOI) technology and consists of four time interleaved ADC cores. It consumes 43 mW overall, while the analog frontend including the four ADC cores and the interleaver consumes only 7.8 mW. In the first Nyquist zone, the effective number of bits (ENOB) is larger than 6.1 bit leading to a Walden Figure-of-Merit (FOM_W) of 45 fJ/conv.-step and a Schreier Figure-of-Merit (FOM_S) of 150.5 dB. Integral (INL) and differential nonlinearity (DNL) are both well below 0.5 LSB for all measurement scenarios.

A PWM-DAC for Analog In-Memory Computing in Mixed-Signal Accelerators

Abstract: This paper proposes the design of a Pulse Width Modulation Digital to Analog Converter (PWM-DAC) for Analog in-Memory Computing. The converter generates voltage pulses, with pulse-width proportional to the 7-bit digital input, in sign-magnitude format. The circuit is designed in a 22-nm FD-SOI technology, with a layout tailored for the severe pitch and area requirements of the memory array for AiMC. The circuit achieves sub-500 fJ/conversion energy consumption, supplied at 0.85 V. The converter obtains an Integral-Non-Linearity (INL) and Differential-Non-Linearity (DNL), normalized at the LSB, lower than 7% and 12%, respectively.

Spin–orbit torque flash analog-to-digital converter

Abstract: Abstract Although analog-to-digital converters (ADCs) are critical components in mixed-signal integrated circuits (IC), their performance has not been improved significantly over the last decade. To achieve a radical improvement (compact, low power and reliable ADCs), spintronics can be considered as a proper candidate due to its compatibility with CMOS and wide applications in storage, neuromorphic computing, and so on. In this paper, a proof-of-concept of a 3-bit spin-CMOS Flash ADC using in-plane-anisotropy magnetic tunnel junctions (i-MTJs) with spin–orbit torque (SOT) switching mechanism is designed, fabricated and characterized. In this ADC, each MTJ plays the role of a comparator whose threshold is set by the engineering of the heavy metal (HM) width. Such an approach can reduce the ADC footprint. Monte-Carlo simulations based on the experimental measurements show the process variations/mismatch limits the accuracy of the proposed ADC to 2 bits. Moreover, the maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.739 LSB (least significant bit) and 0.7319 LSB, respectively.

Design and Implementation of Two-Stage Time-to-Digital Converter Based on Rapid Single-Flux-Quantum Circuits

Abstract: This work proposed a new time-to-digital converter (TDC) utilizing rapid single-flux-quantum circuits. The proposed TDC architecture comprises a counter and a ring oscillator to construct a coarse TDC and a vernier delay line to build a fine TDC, which would maintain the high resolution and high dynamic range of the whole TDC. A TDC with the proposed architecture has been designed, fabricated, and successfully tested. The measurement shows that the designed TDC works correctly with a 5.5 ps resolution, a 1320 ps dynamic range, and a 1.5 LSB differential nonlinearity.

A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration

Abstract: Current-steering DACs are known to be suitable for wideband applications owing to the fast current switching with differential switches and the low output load resistance [1] –[6]. In current-steering DACs, mismatches between the current sources(CS) are the major source of nonlinearity. To reduce the CS mismatch effect, previous works often utilized the Dynamic Element Matching (DEM) [1], [4] or current-source calibration techniques [2], [3], [5], [6]. The DEM randomizes the DAC switching to spread the mismatch tones as noise to improve the SFDR at the expense of increased noise floor, deteriorating the SNR. Background calibration techniques do not have the noise floor issue as they reduce the CS mismatch directly with PVT insensitivity. However, the periodic CS switching operations, disengaging for calibration and reengaging for normal operation, generate unwanted calibration spurs. These spurs can be also randomized as in [6], but the technique still has a disadvantage of increased noise floor near the calibration frequency.

Design and performance of a 16-channel coarse-fine TDC prototype ASIC

Abstract: This paper presents a prototype of a 16-channel Time-to-Digital Converter (TDC) based on the coarse-fine architecture for a small animal Position Emission Tomography (PET) system, which achieves both a large measurement range and high precision. The coarse time stamp is provided by two 12-bit counters, and the duplication of hardware is intended to avoid metastability when the hit signal edge is close to the edge of the counter clock. The fine time stamp is realized with a tunable delay line, which is adjusted by a 32-stage Delay-Locked Loop (DLL) and provides submultiples of the counter clock period. The device has been designed and fabricated in a 180 nm CMOS process. With a 200 MHz system clock, the full-scale measurement range is 20.48μs and the fine bin size is 156 ps. The test results show that the differential nonlinearity (DNL) is between −0.2 to ＋0.2 LSB, and the and integral nonlinearity (INL) is within the range of −0.5 to 0.2 LSB for all 16 channels. The one-shot time precision is better than 60 ps RMS. Power consumption of each channel is less than 8 mW.

A 1.9 ps-rms Precision Time-to-Amplitude Converter With 782 fs LSB and 0.79%-rms DNL

Abstract: Measuring a time interval in the nanoseconds range has opened the way to 3-D imaging, where additional information as distance of objects light detection and ranging (LiDAR) or lifetime decay fluorescence-lifetime imaging (FLIM) is added to spatial coordinates. One of the key elements of these systems is the time measurement circuit, which encodes a time interval into digital words. Nowadays, most demanding applications, especially in the biological field, require time-conversion circuits with a challenging combination of performance, including sub-ps resolution, ps precision, several ns of measurement range, linearity better than few percent of the bin width (especially when complex lifetime data caused by multiple factors have to be retrieved), and operating rates in the order of tens of Mcps. In this article, we present a time-to-amplitude converter (TAC) implemented in a SiGe 350 nm process featuring a resolution of 782 fs, a minimum timing jitter as low as 1.9 ps-rms, a DNL down to 0.79% LSB-rms, and conversion rate as high as 12.3 Mcps. With an area occupation of 0.2 mm2 [without PADs and digital-to-analog converter (DAC)], a FSR up to 100 ns, and a power dissipation of 70 mW, we developed a circuit suitable to be the core element of a densely integrated, faster and high-performance system.