Showing papers on "Interface (computing) published in 1979"

Thoth, a portable real-time operating system

Abstract: Thoth is a real-time operating system which is designed to be portable over a large set of machines. It is currently running on two minicomputers with quite different architectures. Both the system and application programs which use it are written in a high-level language. Because the system is implemented by the same software on different hardware, it has the same interface to user programs. Hence, application programs which use Thoth are highly portable. Thoth encourages structuring programs as networks of communicating processes by providing efficient interprocess communication primitives.

Industrial communications network with mastership determined by need

Abstract: An industrial communications network includes microprocessor-based interface circuits which each connect a controller such as a programmable controller to a high speed serial data link. Each interface circuit connects to the data link and its associated controller, and each is operable to receive messages on the data link directed to its associated controller. In addition, each interface circuit can assume mastership of the communications network when the existing master generates a poll command indicating it is ready to relinquish mastership. As a result, the communications network will continue to function even though one or more controller or their associated interface circuits become inoperable.

Towards an interactive high visual complexity animation system

Abstract: A computer animation system is discussed which employs interactive techniques and presents a unified approach to the graphical display of complex three dimensional data. The system facilitates the generation, manipulation and display of highly detailed data with the aid of interactive devices and a video interface to a standard color TV monitor. The system enables the animator to create a variety of objects (including texture) and to specify the necessary transformations for animation sequences. A run length processing technique combined with a brute force Z-buffer algorithm has been newly designed and implemented that can handle the intersection of several million faces, lines and points. This makes possible a full range of visual cues to simulate fire, smoke, water and complex 3-D texture such as grass, hair and bark. Basic concepts and approaches are described. The display algorithm and the procedure model to generate texture are presented and the implications of the system for computer animation are discussed. Extensions to the system are outlined which include a unique graphics display processor currently under construction that includes a partial implementation of the display algorithm in hardware.

Input/output data processing system

Abstract: An input/output processor architecture for providing an interface between peripheral subsystems and a generalized data processor. The interface processor enables data to be transferred between two address spaces (the generalized data processor address space and an external processor I/O address space) by mapping a portion of the I/O address space into a portion of the GDP address space. This mapping facility provides the peripheral subsystem with a "window" into the associated GDP subsystem. It accepts addresses within a certain subrange, or subranges, and translates them into references into one or more GDP data segments. A function-request facility provides a functional capability over certain objects within the GDP address space. The two facilities provide software on an external processor with a window into the address space of the GDP that enables the software, via the function request means, to send messages to and receive messages from the GDP and to manipulate an environment provided for the external processor within its address space.

The Architectural Features and Implementation Techniques of the Multicell CASSM

Abstract: The architectural characteristics and the implementation techniques of a context addressed segment sequential memory system called CASSM are described. The system provides hardware support for many database management functions. It offers associative and parallel processing capabilities for the efficient retrieval and manipulation of data in large databases. The hardware is designed mainly to support a hierarchical model for database applications but also contains facilities for supporting a wide range of data searches and operations useful for other nonnumeric data processing applications. The software development of the assembly language CASAL and its assembler, the high-level nonprocedural language CASDAL and its compiler, the interface to the CASSM-user interface computer, etc., have been carried out for the system. The hardware design and implementation techniques have been verified using a one-cell prototype system and a simulator designed for testing the system in the multicell environment. The emphasis of this paper is in the detailed description of the hardware features and techniques used in the multicell CASSM system.

Bit by Bit: Toward Decision Support Systems:

Abstract: Alias Decision Support System or DSS, the use of information technology to support upper-level management is receiving much attention. Is DSS just another buzz word-or will it become the system that performs in data storage, access, and handling; analytic model creation, use, and manipulation; and manager-system interface ?

Digital data processing system with interface adaptor having programmable monitorable control register therein

Abstract: A digital system including a plurality of metal-oxide-semiconductor (MOS) chip random access memories (RAM), read only memories (ROM) and peripheral interface adaptors coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU). Each peripheral interface adaptor includes a control register loadable under program control. The contents of the control register control selection of several registers within the interface adaptor. The control register also controls other functions of the peripheral interface adaptor, including determining direction of data movement at the peripheral buffers of the interface adaptor. The contents of the control register of each interface adaptor are monitorable by the microprocessor unit.

Diagnostic-debug machine architecture

Abstract: A system is described for enabling the connection of a diagnostic/debugging processor to another host processor for the purpose of troubleshooting that processor's hardware and software. The system is composed of an interface between the diagnostic/debugging processor per se and the host processor to be diagnosed, and of software resident in the diagnostic processor to perform functions required by the user of the system. The system is specifically designed for use with a host processor utilizing LSSD design rules.

Detachable tool interface system for a robot

Abstract: A mechanical system for allowing removable attachment of tools to a robot which is capable of accommodating positional and angular errors between the tool and the robot during attachment and release of the tool by using tapered attachments.

Computer monitoring system

Abstract: A computer monitoring system connects into the channel, serving as a link between a CPU and peripheral devices. Channel signals are extracted in a channel interface module, altered to be compatible with the logic in a data collection module and sent to a data collection module along with event codes generated within the channel interface module to indicate certain sequences and/or combinations of signals occurring on the channel. The data collection module is programmable to select those peripheral devices it wants to monitor and the type of information to be collected.

Process for monolithic integration of logic, control, and high voltage interface circuitry

Abstract: Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, including various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.

Data distribution interface

Abstract: A microprocessor-based circuit for interfacing between a plurality of serial data terminals and an external parallel data operating system. The interface circuit includes an asynchronous receiver-transmitter, which converts serial data to parallel data and converts parallel data to serial data. The interface circuit multiplexes received serial data from the terminals and couples that serial data to the receiver-transmitter. The microprocessor in the interface circuit further controls the transfer of this now-parallel data to the external parallel data operating system. The microprocessor also controls the transfer of parallel data from the parallel data operating system, which is converted to serial data by the asynchronous receiver-transmitter, demultiplexed by the interface circuit and transmitted to the terminals. Both the transmission and the reception of serial data is coordinated by the microprocessor, which also controls the receiver-transmitter and a set of registers connected to the operating system on a parallel data bus.

Distributed single board computer industrial control system

Abstract: An industrial control system in accordance with the present invention is provided with a plurality of diverse controlled devices (e.g., fans, pumps, valves, solenoids, relays, etc.) for effecting overall system control. Each device has a unique set of logic control functions and/or command sequences and is connected, through an input/output interface, to a stored-program single board computer that provides device control and monitoring. The computers each include a central processor controlled by a composite or "master" program which is common to all the computers and which includes instruction sequences for all logic control functions and command sequences that exist within the system. A user alterable interconnection device (UAID) permits only those logic control function and/or command sequence portions of the master program that relate to a particular one of the controlled devices to operatively connect with the particular input/output ports associated with that controlled device. As the master program successively loops, only those logic control functions and/or command sequences that relate to the particular controlled device, as determined by the user alterable interconnection device, are operative to address the input-output ports associated with the controlled device and thereby effect device control and monitoring. The invention permits simple and efficient dedication of a plurality of single board computers having only one master program to an equal member of diverse controlled devices without the drawbacks normally associated with dedicated stored-program controllers.

I/O Subsystem using data link processors

Abstract: An input-output subsystem for relieving the housekeeping functions of a main host computer and for controlling and transferring data between selected peripheral terminal units and the main host computer. The host computer system connects to a base module through a message level interface bus. The base module houses a plurality of data link processors, each of which controls data transfers to and from a specific peripheral terminal unit. The base module connects all data link processors with a common backplane and provides a distribution control card for connecting and disconnecting selected data link processors to the host system. The base module includes a maintenance card which provides maintenance and diagnostic functions for the data link processors in the base module. Upon initiation of a selected data link processor by the host system and the receipt of an I/O descriptor command, the data link processor then takes on the functions of executing data transfers to and from a peripheral terminal unit and reconnects to the main host system using a descriptor link which identifies the task originally initiated by the host computer system. Upon completion of the data transfer task, the data link processor also sends a result descriptor signal which notifies the main system of the completion, incompletion or error operation of the system. A console unit which includes a microprocessor and program disk is connected to the base module for in-depth diagnostic and checking purposes.

Color graphics display terminal

Abstract: A color graphics display terminal having an edit mode of operation and a graphic mode of operation is disclosed The edit mode provides interactive man-machine interface capability with an external digital computer, such as an automatic test system control computer When operating in the graphic mode it decodes received instructions to produce a multi-colored visual display on a raster scan cathode ray tube color monitor Independent point addressable memories are provided for storing the information to be displayed in the two operating modes Consequently, the information transmitted to the terminal for display in the graphic mode is saved when the terminal is switched into the edit mode and vice versa A key feature is that programs can be edited without destroying the last graphic image produced by the program being edited Data and control commands (such as mode change) are entered into the terminal via a keyboard The terminal is interfaced with the control computer via the industry standard interface (IEEE-488)

Shared storage for multiple processor systems

Abstract: A system is provided that includes a plurality of processors connected to a shared storage via an asynchronous storage interface that includes various interface logic and a ring counter that performs polling of the processors for access to the shared storage. The ring utilizes a "lookahead" feature that bypasses stages in the ring to speed up responses to request signals from the processor. The logic uses the clock from the particular processor accessing the shared memory at any point in time.

Apparatus for providing a course correction signal to an electronic automatic pilot to maintain a vessel on a predetermined geographic course

Abstract: A system for controlling the course of a vessel. A digital computer 22 receives information signals from a geographic position locator 20, such as a Loran-C receiver, a depth sounder, or a water temperature sensor, and is also capable of interactive communcations with a remote terminal 24 which is accessible by an operator of the vessel. The digital computer 22 continuously monitors the information signals and develops therefrom a digital output signal representing the sign and magnitude of vessel cross-track error. To obtain information required to determine cross-track error, and to obtain certain other information relating to the identity and type of the geographic position locator 20, the digital computer 22 transmits questions to the remote terminal 24 for display therby and evaluates responses made by the operator through remote terminal 24. The digital computer 22 may be enabled or disabled in response to instructions from the operator using remote terminal 24. The digital computer 22 may also be disabled during the existence of an alarm condition resulting from instability in the information signals, or upon detection of information in the information signals representing loss of tracking by the geographic position locator 20. An interface unit 30, which is enabled only when the digital computer 22 is enabled, converts the cross-track error information in the digital output signal into a corresponding analog cross-track error signal. After suitable amplitude scaling, the analog cross-track error signal is integrated, and the integrated signal is summed with the analog cross-track error signal, to develop a course correction signal which is adapted to be summed with a heading error signal in a conventional electronic automatic pilot, whereby the electronic automatic pilot is capable of maintaining the vessel at a desired heading and on a predetermined geographic track.

Standard Specification for S-100 Bus Interface Devices

Abstract: This proposed standard eliminates many of the problems in the S-100 bus and upgrades it for 16-bit microprocessors. It is offered here for public comment before submission to the IEEE Standards Board.

Distributed function communication system for remote devices

Abstract: To effect an accurate transmission of data between processing equipment and a plurality of peripheral devices, first and second interfaces are employed for reconstructing and transmitting the data over a communications link such as a conductor pair. The first interface termed a master terminal which is coupled to a common control module by way of a common control bus, receives instruction, address, and data information from the processor, and transmits a serial data code containing all this information to a plurality of second interfaces, termed slave terminals. Each slave terminal is coupled to a set of peripheral devices by a common bus and when a peripheral device recognizes its address being present in the code received from the master terminal, the slave terminal responds to complete the transaction with the master terminal and the addressed peripheral device.

Advanced mobile phone service: Cell-site hardware

Abstract: The hardware facilities of the amps cell site connect the mobile radio customer to the land telephone network and perform actions necessary for rf radiation, reception, and distribution; voice and data communications and processing; equipment testing, control, and reconfiguration; and call setup, supervision, and termination. Cell-site operational control is achieved partially through wired logic and partially through programmable controllers. This paper describes the cell-site functional groups, their physical characteristics and design, and the ways they interface with the rest of the amps system.

Processing of information

Abstract: A handwriting recognition device comprises a transducer surface responsive to a pen positioned thereon for representing the coordinate position of the pen as an electrical signal, and data processing means for recognizing a handwriting effected with the pen, the data processing means including a microprocessor based control controlling a read/write memory, a non-volatile read-only memory storing a handwriting recognition routine to store recognized handwriting in the read/write memory, and an interface communicating to a host computer system a representation of the recognized character. A visual display may be provided coupled to a display interface and an input information for receiving verified recognized handwriting communicated from the host computer system. The read/write memory has a first storage location coupled to the transducer storing a representation of signals from the transducer, a second storage location coupled to the interface and storing a representation of recognized handwriting, and a third storage location coupled to the display interface and storing an image of the display.

Data link processor for magnetic tape data transfer system

Abstract: A peripheral controller, designated as a data link processor, is used for linking a main host computer system with a plurality of magnetic tape transport units. Upon receipt of instructions from the main host system, the data link processor will initiate operations for the sending and receiving of data from a plurality of magnetic tape units and relieve the main host system of all housekeeping functions required for data transfers. The data link processor is made up of two units which may be mounted on separate slide-in printed circuit cards. The first unit is a standardized common unit for all types of data link processors and is known as the Common Front End. It provides micro-code storage which is used to effectuate various read, write, control and transfer operations. The second unit is designated as a Peripheral Dependent Board providing the transmission-reception interface to the peripheral magnetic tape units.

Mechanical and electrical connection interface for a battery containing pack

Abstract: A connection interface for mechanically and electrically connecting a battery containing pack and a battery utilizing device includes a plurality of outwardly facing lugs positioned on the battery pack to define outwardly facing tab-receiving slots Cooperating inwardly facing tabs located on the battery utilizing device define inwardly facing lug-receiving slots such that the outwardly facing lugs are received within the inwardly facing lug-receiving slots and the inwardly facing tabs are received within the outwardly facing tab-receiving slots The mating faces of the tabs and lugs are inclined relative to a medial plane to accomodate accumulated tolerances and assist in providing a rigid mechanical connection A manually operable latch is provided to prevent unintentional separation of the battery pack and the battery utilizing device

Output interface card suitable for use with a programmable logic controller

Abstract: A programmable logic controller includes a plurality of input interfaces and a plurality of output interfaces for connection to industrial equipment such as automatic assembly equipment, textile machinery, materials handling equipment, and chemical processes. The input and output circuits can be randomly addressed as to their state through an eight bit bus, which connects in parallel with up to 16 groups of eight input and/output circuits. The controller includes groups of timers which are each manually adjustable as to the timing operation and which are sequentially addressed each time a timing function is called for by the program. The timers are designed to be cascaded in groups to virtually any number of timers. The controller includes a scratch pad memory, half of which retains memory upon power failure and half of which does not. The control of the controller by the operator is made more nearly foolproof by interlocking the operations of control switches. Three programming instructions are available which are conditional upon the data in the accumulator of the controller.

Microprocessor-controlled EDM system

Abstract: An EDM parameter control system comprising a microprocessor having a memory for storing therein a programmed set of microinstructions representing selectable values for each of the EDM parameters. A gap monitoring circuit derives from the EDM gap a gap status signal representing characteristics thereof, the gap status signal being applied through an input interface to the microprocessor wherein it is used to microprocess the previously stored parameter data to provide control signals applicable to respective control devices for regulating the machining parameters (e.g. machining pulse on-time and off-time, gap spacing, tool reciprocation commands, dielectric supply control parameters). Preferably, the parameters are weighted in microprocessing and the output interface is constituted by a time-sharing unit for actuating the control devices in preset time divisions.

Versatile microprocessor bus interface

Abstract: There is provided a microprocessor interface circuitry which allows single peripheral and memory devices to be used with at least two different types of microprocessors. The interface includes a latch which latches the state of a control signal provided to the peripheral/memory device by the microprocessor. The control signal that is latched serves a somewhat different function when eminating from each of the at least two different microprocessors, and as such has different logic states. Logic circuitry is controlled by the latch to take at least one other control signal and generate the internal control signals used by the peripheral/memory device.

Computer Network Architectures

Abstract: This tutorial analyzes developments in computer network architectures from a top-down design viewpoint—starting with user interface requirements, then developing a structure to realize that interface.