Showing papers on "Logarithmic number system published in 2019"

FPGA realization of a speech encryption system based on a generalized modified chaotic transition map and bit permutation

Abstract: This paper proposes a generalized modified chaotic transition map with three independent parameters. A hardware speech encryption scheme utilizing this map along with a bit permutation network is presented. While the transition map’s generalization introduces additional parameters, the modification enhances its chaotic properties and overcomes the finite range of the control parameter and dynamical degradation problems. The modification also presents a simplification for the hardware realization of the exponentiation operation in the map’s equation because the modified output range allows conversion from the linear domain to the Logarithmic Number System (LNS). Mathematical analysis of the map is presented, where exact nonlinear expressions of the dependent parameters are derived and validated through simulations. To further simplify the hardware realization, the complicated nonlinear expressions are linearized and the introduced approximation error is quite acceptable. The encryption scheme is simulated using Xilinx ISE 14.7 and realized on Xilinx Nexys 4 Artix-7 FPGA with a throughput of 1.526 Gbit/sec. The security and efficiency of the hardware speech encryption scheme are validated and the performance is compared with recent works that provided experimental results on Pseudo-Random Number Generation (PRNG) and speech encryption.

An Improved Logarithmic Multiplier for Media Processing

Abstract: As the modern computing systems become increasingly embedded and portable, a growing set of applications in media processing (graphics, audio, video, and image) has evolved. Multiplication is the operation that is most often used in these applications which when accomplished in logarithmic number system results in an area efficient and faster design. In this work, the authors describe a technique that combines Mitchell's approximation with a novel hardware truncation scheme resulting in an iterative multiplier with improved precision and reduced area. Further, a new fractional predictor combined with an existing truncated logarithmic shifter significantly reduces the overall hardware cost of the multiplier. Simulations carried out on benchmark image processing applications such as Lena, cameraman and pirate clearly indicate that the proposed technique performs better than those available in the literature.

Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs

Abstract: FPGAs have been successfully used for the implementation of dedicated accelerators for a wide range of machine learning problems. The inference in so-called Sum-Product Networks can also be accelerated efficiently using a pipelined FPGA architecture. However, as Sum-Product Networks compute exact probability values, the required arithmetic precision poses different challenges than those encountered with Neural Networks. In previous work, this precision was maintained by using double-precision floating-point number formats, which are expensive to implement in FPGAs. In this work, we propose the use of a logarithmic number system format tailored specifically towards the inference in Sum-Product Networks. The evaluation of our optimized arithmetic hardware operators shows that the use of logarithmic number formats allows to save up to 50% hardware resources compared to double-precision floating point, while maintaining sufficient precision for SPN inference at almost identical performance.

One-Hot Residue Logarithmic Number Systems

Abstract: Switching behavior and dynamic power consumption of arithmetic circuits are influenced by the distribution of operands as well as the number system used to encode them. Binary integer encoding may cause severe switching fluctuation; the integer Residue Number System (RNS) reduces this by breaking the integer into smaller moduli, which in turn may use either binary or one-hot encoding. One-hot switching is nearly consistent regardless of operand distribution, but this comes at the cost of increased bit width. Reals are represented by mapping integers, such as well-known examples of fixed point and Floating Point (FP). A more unusual system is the Logarithmic Number System (LNS) that takes the logarithm of the absolute value of the real (its sign is encoded separately) into an integer. Combining one-hot, RNS and LNS offers real arithmetic circuits with nearly uniform switching at the cost of some complexity in word size, addition, conversion and sign-detection.

Optimizing Mitchell's Method for Approximate Logarithmic Addition via Base Selection with Application to Back-Propagation

Abstract: Mitchell's method typically is used to compute approximate base-2 antilogarithms using minimal hardware (no ROM). Another use of identical hardware approximates the function (called the “addition logarithm”) that computes the sum of values represented by the Logarithmic Number System (LNS). Since Mitchell's method was originally conceived for base-2 antilogarithms, the previous usage of Mitchell's method for LNS addition also considered only base-2. For applications where approximate arithmetic is viable, there is little need for compatibility with standard base-2 arithmetic, such as IEEE-754. Therefore, the LNS base, $b$ , is a design parameter that can be optimized without increasing the hardware cost. Previous optimization of the LNS base (trading range and precision) was implemented with ROM (ideal accuracy), but no previous work has optimized the base for a ROM-less (lower accuracy) Mitchell LNS. Assuming a uniform distribution, we derive $b\approx 2.09$ as optimal for Mitchell LNS addition; however, in actual applications, like machine learning, searching for the application-specific base yields a low-cost Mitchell implementation of back-propagation that converges as successfully as a more expensive IEEE-754 implementation.

"Vector Arithmetic Unit Design Using FXP-HNS Technique for Power, Delay and Area optimization"

Abstract: In 3D handheld graphics processors, Vector arithmetic unit is an unavoidable part for vector operations. The handheld devices are small screen devices. The resolution of it is less but its power and area must be optimized while designing. For these devices, vector operations can be done with fixed point hybrid logarithmic number system technique (FXP-HNS). This technique gives faster operations with optimized power, delay and area. We are proposing hardware which is compatible for vector operations like Additions / Subtractions, Multiplication/ Division, Square-root. for 32-bit Fixed point Hybrid Logarithmic number system format input in Xilinx 14.7 tool.The proposed designed hardware verified on 180nm, 90nm and 45nm technologies using CADENCE Encounter tool. The respective total power requirements are 820.5µw, 239.8µw and 116.7µw for 180nm, 90nm and 45nm technologies. The time requirements for operations are 20590ps, 15036ps and11383ps respectively.The proposed hardware gives optimized & efficient results with 45nm technology for vector arithmetic operations. Which is also efficient for Fixed point (FXP) and Floating point (FLP) operations with programmable arithmetic pointer in FXP-HNS technique..

Optimization of the Hardware Costs of Interpolation Converters for Calculations in the Logarithmic Number System

Abstract: The logarithmic number system (LNS) is an advanced alternative to the widely known in a computer technology representation of floating-point numbers. It provides greater accuracy and speed of computation with a comparable range of representation of numbers. However, the widespread use of LNS is prevented by the need to apply interpolation to convert numbers from the traditional format and back, and to perform addition/subtraction operations. Known solutions are oriented to interpolation by a first-order polynomial, which does not allow the use of double or quadruple precision due to exponential growth of hardware costs. The work is devoted to minimizing hardware costs by optimizing the order of the interpolation polynomial and the interpolation step for computations over numbers of different width. The results of the work can be used to develop arithmetic devices that operate with numbers in the LNS and are optimized for the level of hardware costs.

Design of High-Speed and Area-Efficient Cartesian to Polar Coordinate Converters Using Logarithmic Number Systems

Abstract: In this work, high-speed and area-efficient rectangle to polar coordinate converters are proposed. By adopting logarithmic number system (LNS)-based implementations, tremendous and time-consuming operations for obtaining the values of radius and angles from given values of Cartesian coordinates can be easily simplified and implemented. Simulation results show that our proposed design can achieve area-delay efficient than conventional designs with tolerable errors. The proposed converters can be applied in real-time signal processing applications.

Under- and Overflow Detection in the Residue Logarithmic Number System

Abstract: The Residue Number System (RNS) offers fast and cheap carry-free integer arithmetic but has slow and expensive overflow detection. The Logarithmic Number System (LNS) offers fast real multiplication, division and powers with floating-point-like relative precision. The Residue Logarithmic Number System (RLNS) is a combination of the two systems that offers advantages for moderate-precision real applications where a-priori analysis allows under-and overflow to be ignored. An arithmetic hardware generator is essential because of the mathematical obscurity of combining RNS and LNS. Unfortunately, real applications often underflow. We consider options to deal with under-and overflow using the RLNSTool generator as a foundation.

An Area Efficient 16-bit Logarithmic Multiplier

Abstract: Digital signal processing applications often use major mathematical operations such as multiplication, which consume more power and time. Operations like Fast Fourier Transform, Convolution and correlation depends heavily on a large number of multiplications. There are many techniques available to perform multiplications. One such technique is logarithmic multiplication. logarithmic multiplication is achieved by adding the binary logarithms of two numbers and deriving the antilog of the result. In this paper, an efficient algorithm for logarithmic multiplication is presented with the use of adders, decoders, multiplexers and a few combinational circuits that effectively reduce the power and area of the multiplier.