Showing papers on "Logic level published in 1973"

MOS power-on reset circuit

Abstract: An automatic power-on reset circuit adapted for use on complementary MOS integrated circuit semiconductor dies is provided. The circuit includes a voltage reference stage followed by an amplifier stage. A PN diode is coupled in series with a diode-connected MOSFET and a low current MOSFET device to provide a slight overdrive to the P-channel MOSFET of a CMOS inverter, which determines the initial output level thereof. As the voltage applied to the power supply conductor increases, the switching point of the amplifier-inverter stage varies until the output thereof assumes the opposite logic level. This transition of the output of the amplifier inverter stage is applied to wave shaping circuitry and an output circuit which reliably produces the desired reset signal.

Computer-aided prediction of delays in LSI logic systems

Abstract: A computer program is described which was developed for LSI (large scale integrated) systems to resolve the uncertainties in transient delays prior to building the physical logic systems This computer program represents a departure from the conventional logic simulation programs where unit delays are assumed for individual logic elements The program takes into account all physical circuit variables at the mask composite stage in the design cycle Transient delays are computed and inserted into the logic simulation program

Emitter function logic-logic family for LSI

Abstract: A highly efficient large-scale integration logic family combining the advantages of multiemitter structures with the performance of emitter-coupled logic is discussed. Simplified gate structure has been found to reduce propagation delay, power and number of logic levels required for logic function realization. Conventional processing affords 2-5-pJ performance. The principle of operation of a basic AND-OR gate is shown and compared with the well known ECL gate. Fundamental gating and sequential logic functions are compared with the conventional inverting designs. The solid-state realization of a test gate is described. The speed-power performance advantage of emitter function logic gates and functions are contrasted with those of presently popular logic families.

Digital transmitter for data bus communications system

Abstract: Disclosed is an improved digital transmitter for transmitting serial pulse-code modulation (pcm) data at high bit rates over a transmission line. When not transmitting, the transmitter features a high output impedance which prevents the transmitter from loading the transmission line. The pcm input is supplied to a logic control circuit which produces two discrete logic level signals which are supplied to an amplifier. The amplifier, which is transformer coupled to the output isolation circuitry, converts the discrete logic level signals to two high current level, ground isolated signals in the secondary windings of the coupling transformer. The latter signals are employed as inputs to the isolation circuitry which includes two series transistor pairs operating into a hybrid transformer functioning to isolate the transmitter circuitry from the transmission line. An effective increased amplitude, balanced, differential output signal is produced by the transmitter from the serial pcm input data to provide an improved transmitted signal to the transmission line.

Comparison of MOSFET logic circuits

Abstract: Linear load, depletion-mode load, four-phase dynamic, and complementary MOSFET logic circuits are compared on the basis of power, delay, and density for two specific master slice layouts. The circuits were designed in a common technology base, and normalized power and delay characteristics were calculated by simulation. Chips of 1280 circuits were designed in images having one and two layers of metal, and power versus delay curves were calculated. The effect of an insulating substrate was also considered.

Configurable communications controller having shared logic for providing predetermined operations

Abstract: The apparatus of the invention includes receive logic for converting serial bit characters to parallel bit characters and transmit logic for providing a parallel to serial bit character conversion. The receive and transmit logic are coupled between a processor and a communication line. Both the transmit and receive logic are coupled with a code unit which performs specified logic operations in response to the identity of the characters either received or transmitted. The apparatus is easily configurable for different bit length characters and the code unit is time-shared by the transmit and the receive logic.

Level shifter transistor for a fluorescent lamp ballast system

Abstract: An improved arrangement for coupling logic drivers to power devices in a solid-state fluorescent lamp ballast system in which the necessary isolation between the high voltage power devices in the solid-state ballast system and the logic drivers is obtained by using level shifter transistors in which the power switch to be isolated is selected to be a PNP transistor and the transistor for driving and isolating the PNP transistor is an NPN level shifter transistor.

Threshold logic gate

Abstract: A threshold logic gate is utilized for parity checking by providing two double threshold detectors responsive to logic levels provided by a level shifter which shifts the logical voltage levels produced by a differential amplifier which sums the four inputs.

Fully-compensated emitter-coupled logic: Eliminating the drawbacks of conventional ECL

Abstract: New approaches to high-speed emitter-coupled logic circuitry, overcoming system drawbacks by eliminating sensitivity to environmental changes, are discussed. A comparison is made with uncompensated conventional ECL. Circuits displaying threshold and level invariance over wide ranges of ambient temperature, typically greater than 0/spl deg/-75/spl deg/C, and supply voltage, -4.7 to -6.2 V, are described. Suggestions are made as to how these features can lead to higher performance, and at the same time, lower cost systems.

Logic circuit arrangement using insulated gate field effect transistors

Abstract: A logic circuit arrangement includes a first transistor having the source-drain conduction path connected between a first power source terminal and an output point and rendered conductive in response to a clock pulse applied to the gate electrode, and a plurality of second transistors, constituting at least one logic gate, each having the source-drain conduction path connected between the output point and a second power source terminal and the gate electrode supplied with a logic input. The arrangement is such that current is not concurrently flowed between the first power source terminal and the output point and between the output point and the second power source terminal. The source-drain conduction path of a third transistor is further connected between the first power source terminal and a junction of the adjacent two transistors in the logic gate and rendered conductive, during the conduction of the first transistor, in response to a clock signal applied to the gate electrode, so that a voltage of the output point indicates a predetermined level corresponding to a logic ''''1'''' or ''''0'''' irrespective of the difference of operation mode of each transistor.

EFL logic family for LSI

Abstract: A highly-efficient LSI logic family combining the advantages of multi-emitter structures with the performance of ECL logic will be discussed. Simplified gate structure has been found to reduce propagation delay, power and number of logic levels required for logic function realization. Conventional processing affords 2-5 pJ performance.

Adaptive logic circuits for digital stochastic computers

Abstract: A theoretical and experimental investigation of adaptive logic elements suitable for use as an output interface for digital stochastic computers is presented. An adaptive digital element using a binary rate multiplier is demonstrated to provide a significant improvement in accuracy without reduction in bandwidth characteristics.

Process for stress testing FET gates without the use of test patterns

Abstract: A testing process is described for stress testing each gate electrode in a dynamic random logic FET circuit array incorporated in an LSI device. The process comprises the steps of providing operating potentials and clock signals to each logic circuit in a logic path in the LSI device; providing a stress voltage to each initial logic element in a logic path, and sequencing the clock signals to each logic circuit in reverse order to that sequence required to transfer information through a logic path to perform the circuit logic function. The invention advantageously utilizes the fact a reverse clock will sequentially stress each logic circuit while in a discharge state and the other logic circuits are in a non-conducting condition.

Digital filter circuits

Abstract: An intrusion alarm system for providing an alarm indication in response to the detection of an intruder within a protected area includes Doppler radar apparatus having a transmitter for radiating energy into the protected area, a receiver for receiving Doppler signals provided whenever radiated energy is reflected off a moving body within the protected area and a signal detecting and filter circuit having a level detector circuit and a low pass digital filter circuit responsive to Doppler signals in excess of a predetermined amplitude and frequency to provide a logic level output indicative of the detection of an intruder within the protected area. In addition to the low pass digital filter circuit, there are described a high pass digital filter circuit and a digital band pass filter circuit.

A TTL compatible threshold gate

Abstract: A threshold gate circuit is presented which permits a large number of input weights with good noise margins. This is done by replacing the usual voltage detector with a current detector. Results of testing an experimental ten input model are given.

Shared Logic Realizations of Dynamically Self-Checked and Fault-Tolerant Logic

Abstract: Dynamically self-checked or fault-tolerant realizations of switching functions and sequential machines are proposed under a fault model that permits arbitrary logic faults in a single-logic module, where the modules are explicitly defined These realizations permit considerable logic sharing, organized around an (n, m, r)-basis for decomposing switching functions The logic sharing permits more economical realizations than can be obtained using classical parity and triple-modular redundancy schemes for obtaining logic circuits with the corresponding property

Precharged digital adder and carry circuit

Abstract: Disclosed is a calculator system featuring a precharged carry propagate arithmetic logic circuit. A plurality of data registers store in parallel a plurality of multi-bit data words and are coupled in parallel to the arithmetic logic circuit for executing arithmetic and logic operations thereon. The arithmetic logic circuit is responsive to instruction words for executing either an addition or a subtraction function. A carry propagate circuit is provided for precharging a carry terminal of each bit in the ALU to a reference potential along with a circuit associated with each bit for selectively discharging the carry terminal responsive to the logic level of the previous carry signal into each bit and is further responsive to the appropriate bits of the data words. An exclusive-or adder circuit has an adder terminal precharged to a reference potential during one phase of a clock signal, and further has a discharge circuit for selectively discharging the terminal in response to logic levels of the appropriate bits of the data word and responsive to the carry signal.

Superintegrated voltage clamp

Abstract: A monolithic implementation of a voltage clamp circuit is described that saves area and reduces capacitance, as the transistor and the voltage divider resistor required are merged into a single device Following this principle in current switch logic circuits, even the emitter follower can be superintegrated into the collector loads Moreover, base-bleeding resistors can be incorporated in transistors of silicon-controlled rectifiers

Rise time of emitter-coupled logic circuits including the effects of collector-to-base capacitances

Abstract: Rise times of emitter-coupled logic circuits are computed, taking into account collector-to-base capacitances as well as gain-bandwidth products, ohmic base resistances, external stray capacitances, and the finite rise time of the input signal. Basic considerations are discussed, and explicit expressions and graphs are given for a wide range of circuit parameters.

Fractional Frequency Synthesizer

Abstract: A simple technique is presented for using standard IC logic elements to synthesize frequencies. In particular, certain fractional multiples of a primary frequency may be synthesized for which no convenient techniques are available at digital logic levels. By utilizing the harmonic content of repetitive digital waveforns, sum and difference frequencies may be extracted from the output of the digital logic network. In effect, the new technique provides a type of digital mixing to accomplish frequency synthesis (or conversion) which is compatible with modern digital circuits. The circuit complements available techniques for division by an integer.

Serial residue generator for use in a self-checking computer

Abstract: This letter describes a serial circuit for generating the residue of a binary number. The object is to produce circuits compatible in speed with most small computers, so that the number of logic gates required is greatly reduced compared with a parallel mode of residue generation.