Showing papers on "Master clock published in 1984"

Timing system for laser disc having digital information

Abstract: A timing system is disclosed for reading symbol sites, analog or digital from a video signal preferable in a recorded laser format. A video signal having analog data events at precise timed intervals is recorded on a first commercial grade video recorder. The tape is replayed through a second commercial grade recorder to an optical lathe. At the time of playback to the optical lathe, a timing signal is derived from a phase lock loop circuit added to the second commercial grade and recorded on the FM band of the video signal, which signal is then etched by the lathe onto a master optical disc. Simultaneously with the recordation of the substantially continuous FM band, selected horizontal scans on each frame are loaded with both timing and reference level data, the timing portion of these selected scans being later used for phase comparison of the signal. An optical disc master results which has a continuous FM band timing track as well as an interleaved timing information contained in the video signal. Replication from the optical master to stamped copies occurs with the stamped copies being distributed to discrete players for data access. At each player, the continuous FM band timing track is used for the master clock. This continuous clock cycles a ramp generator with each clock pulse. Phase synchronization is taken from the selected horizontal scans distributed through each frame by having a phase comparator change the sample level of the cycled ramp. The changed level of the cycled ramp adjusts the phase of the master clock pulse. Precise readout of analog symbol event occurs in precise timed and phase corrected.

A novel clocking technique for VLSI circuit testability

Abstract: Scan-testable digital designs have a special `scan' operating mode to set and read the states of flip-flops in the circuit. All previous scan-testable design implementations required at least one additional input pin to specify either scan or normal operating mode, and this mode specification signal had to be routed to every flip-flop. A new clocking structure is described which eliminates these requirements for certain designs with static flip-flops that are controlled by two independent signals (master clock and slave clock). This is possible because, in normal circuit operation, the master and slave clocks are never simultaneously active. The new clocking structure uses the `all clocks active' condition to specify the scan mode. Implementation of the concept is discussed in detail for two-clock circuits. Single-clock circuits can be modified to use this scheme, and the results for this class of design are also presented.

Method and apparatus for generating phase locked digital clock signals

Abstract: @ A method and apparatus for generating two phase locked digital clocks of different word rates particularly suited for a graphic and alphanumeric computer display terminal. Master and slave clock generators are used to generate output pulses at every N-th and M-th clocks of a common clock. A phase lock loop including the master clock generator and a phase lock counter dividing the common clock by the factor of the least common multiple of N and M is used to synchronize the slave clock generator.

Circuit arrangement for clock generation in communication installations, especially TDM digital exchanges.

Abstract: of EP01000761. A circuit arrangement for telecommunications systems, in particular PCM telephone exchange systems, with a duplicated exchange clock supply arrangement (CCG', CCG") in which the respective first of the two exchange clock generators supplies an exchange clock signal (T', T") which is generated independently of the respective other exchange clock generator, and the respective other (slave) exchange clock generator supplies an exchange clock signal which is synchronised so as to be at least approximately in phase with the exchange clock signal supplied by the respective first (master) exchange clock generator, and in which each of the two exchange clock generators, servo-synchronised by a supplied master clock signal (M', M"), generates an intermediate clock signal (H', H") with a clock period which at the maximum is equal to the maximum permissible phase difference between the exchange clock signals supplied by the two exchange clock generators, and in which, in each of the two exchange clock generators, the intermediate clock signal is supplied to a respective frequency divider (BKU, U) for the acquisition of the exchange clock signal, and in which the respective slave exchange clock generator compares its exchange clock signal with the exchange clock signal of the respective master exchange clock generator (PD) and when a phase difference is established which exceeds a limit value in the order of one intermediate clock period (h) by means of a regulating device in the case of a lagging slave exchange clock signal shortens-and in the case of a leading exchange clock signal lengthen-one half period of the slave exchange clock signal by the length of one intermediate clock period, and in which the exchange clock signal supplied by the respective master exchange clock generator is monitored and in the event of the failure thereof the regulating device of the hitherto slave exchange clock generator is disconnected, whereby the hitherto slave exchange clock generator now becomes the master exchange clock generator whose exchange clock signal is now supplied to the hitherto master exchange clock generator which has now become the slave exchange clock generator, characterised in that when it establishes a leading or lagging of the initially slave exchange clock signal the regulating device (UVR) of the initially slave exchange clock generator lengthens or shortens respectively the half period of the exchange clock signal supplied by itself with a time delay which is at least equal to the time interval required to disconnect the regulating device of the slave exchange clock generator in the event of the failure of the master exchange clock signal.

Maintenance of time and frequency in the Jet Propulsion Laboratory's Deep Space Network using the Global Positioning System

Abstract: : The Deep Space Network (DSN), managed by the Jet Propulsion Laboratory for NASA, must maintain time and frequency within specified limits in order to accurately track the spacecraft engaged in deep space exploration. The DSN has three tracking complexes, located approximately equidistantly around the earth. Various methods are used to coordinate the clocks among the three complexes. These methods include Loran-C, TV Line 10, Very Long Baseline Interferometry (VLBI), and the Global Positioning System (GPS). The GPS is becoming increasingly important because of the accuracy, precision, and rapid availability of the data; GPS receivers have been installed at each of the DSN complexes and are used to obtain daily time offsets between the master clock at each site and LTC (USNO/NBS). Calculations are made to obtain frequency offsets and Allan variances. These data are analyzed and used to monitor the performance of the hydrogen masers that provide the reference frequencies for the DSN Frequency and Timing System (DFT). This paper contains: (1) a brief history of the GPS timing receivers in the DSN, (2) a description of the data and information flow, (3) data on the performance of the DSN master clocks and GPS measurement system, and (4) a description of hydrogen maser frequency steering using these data.

Synchronizing system of digital multiplex transmission system

Abstract: PURPOSE: To receive data without changing a reception timing at a main controller by providing a phase control function to propagation delay to each terminal device connected to two pairs of cables in the form of multidrop. CONSTITUTION: A reference clock and a transmission data from a master clock oscillator 13 in the main controller are transmitted to a cable 3b via a signal transmission circuit 15. A signal reception circuit 10 of each terminal device receives the reference clock, a loopback pulse extracting circuit 6 separates a synchronous pulse and reception data and a reception PLL circuit 11 extracts the reception block. The synchronous pulse extracted from the circuit 6 becomes a loopback pulse, which is subjected to phase comparison with the reception block at a phase comparator circuit 7, the compared output is subjected to a delay in response to the propagation delay of a cable length by a variable delay circuit 8 to form a transmission clock at the terminal device. The transmission clock is transmitted to a cable 3a via a phase control pulse transmission circuit 5 and a signal transmission circuit 9. A signal reception circuit 12 of the main controller receives the synchronous pulse in the same phase from each terminal station. COPYRIGHT: (C)1986,JPO&Japio

Device for detecting linear velocity of recording track of recording disk

Abstract: PURPOSE:To integrate easily the titled device without using capacitor and, at the same time, improve the reliability of the device, by generating edge pulses synchronously to a frequency which is integer times as large as a clock signal for demodulation by detecting the leading edge and trailing edge of the signal and detecting the linear velocity of a recording track in accordance with the outputted content of each stage of a shift register. CONSTITUTION:A read EFM signal B is inputted into a PLL circuit 1 and a self-clock for demodulation contained in the signal B is extracted and sent to a demodulating section. The signal B becomes the data input of a DFF 2 and each Q-output C and D of the DFFs 2 and 3 becomes two inputs of an exclusive OR gate 4. A reference clock signal A having a frequency 2f which is twice as large as a master clock for demodulation is generated from a clock signal generator 5 and the DFFs 2 and 3 are operated and, at the same time, the shifting operation of a shift register 6 composed of 47 stages is controlled. The frame sink pattern length is detected by the shift register 6. Since the content of the shift register 6 varies in accordance with the linear velocity, the linear velocity can be detected by discriminating the content of the shift register 6.

Area measuring device

Abstract: PURPOSE:To measure the area of a pattern to be measured quickly and accurately by an easy operation, by calculating the area on a basis of a picture signal which is obtained by moving a linear image sensor on the plane of the pattern to be measured. CONSTITUTION:An image sensor 10 latches the electric charge, which is proportional to the density of each picture element, in a register by a start pulse (c) and shifts it in serial at the timing of a shift pules (d) to output an analog picture signal. A picture signal (e) amplified by an amplifier 15 is converted to a binary signal (f) by a threshold TH. A master clock pulse (a) and a signal (f) are inputted to an AND gate 17 to output a signal (g). An operating circuit 18 counts the clock pulse (g) and uses the counted value to execute the arithmetic, thus calculating the area of the pattern to be measured.

Investigation and design of a controller of an asynchronous system for fault-tolerant aircraft control using hybrid voting techniques

Abstract: The paper presents an investigation into the design and operation of an intelligent controller for a multimicroprocessor-based fault-tolerant aircraft control system. This unit, called an asynchronous consistency unit (ACU), uses an interactive procedure and a mutual feedback mechanism (called synchronisation voting) for the timing control of the exchange of data among processors. Fault tolerance is achieved by majority voting of the exchanges between various processors. This is implemented by using both hardware and software techniques (hence the name hybrid). The ACUs govern the reliable operation of the system so that no module failure (processor, ACU or bus) has hard core characteristics; i.e. it cannot affect the reliable operation of the system, causing a catastrophic failure. The design provides full fault assertion for the ACUs and notification of failures to the processors. An ACU requires no master clock operation and it operates independently of its host processor in an asynchronous mode. A four-module system is presented. A disadvantage of this design is that the total number of data and control lines of the bus is substantial. If N data bits are exchanged in a four-module system, the total number of lines in the ACU is at least 4N+32. This disadvantage is, however, offset by the stringent requirement of full system fault tolerance in both the data and control signals of the aircraft control system.

Bit clock regenerating device

Abstract: PURPOSE:To obtain a regenerated data signal of high quality by detecting the center part of a bit of a data signal, detecting the relative position with a bit clock signal for perforation, and performing perforation near the center of the bit all the time by the detection signal. CONSTITUTION:A bit center detection part 1 receives a data signal containing jitters and a master clock signal C. Its output is sent to center comparators 2, 3, and 4 to generate the difference from the position of a bit clock for perforating a bit center from the output of the detecting part 1 and the output of a 1/6 frequency divider 5. The outputs of those comparators 2, 3, and 4 and the signal are supplied to the frequency divider 5 to send out a bit clock signal B positioned in the center of each bit.

System trouble detector

Abstract: PURPOSE:To detect a break of a master clock and a software fault due to a program runaway through small-sized hardware by flowing the clock to a linked CPU, and putting respective CPUs in software processing and only the final CPU in charge of hardware processing CONSTITUTION:When the master clock CLK1 of a CPU1 is broken, an input B to and an output B from a frequency divider 30 are both at constant levels Consequently, outputs C and D of CPUs 2 and 3 are at constant levels and a detecting circuit 20 generates an alarm output ALM On the other hand, when a master clock CLK2 or CLK3 is broken, neither the CPU 2 nor 3 operates and the output D becomes constant, so that the detecting circuit 20 generates the output ALM Further, if a program runaway occurs to the CPU2 or CPU3, the period of the pulse signal C or D can not be held constant even when the master clocks CLK1-CLK3 are all normal Consequently, the output E of the break detecting circuit 20 varies when the period of the input D becomes long, thereby generating the alarm-level output

Relative moving speed control device of information detecting point in information reader

Abstract: PURPOSE:To eliminate the read error of a data due to a temperature drift by using a master clock utilizing a quartz crystal resonator, and setting the time width of a speed control pulse without using a resistance and a capacitor for setting timing. CONSTITUTION:An FF1 becomes a set state at the time of rise of the first master clock (a) after a reproducing synchronization signal (b) is generated. The FF1 becomes a reset state at the time of rise of the first master clock (a) after the reproducing synchronizing signal (b) is annihilated. A clear signal (e) is supplied to a counter CT1 from an NAND gate G1 supplied with a Q output (c) and a Q' output (d). When the counting value of the counter CT1 becomes 15, a carry output (f) consisting of a high level signal is generated. At the time of rise of the master clock (a) after the output (f) is generated, the counting value of the counter CT1 is reset to ''0'' and the output (f) is annihilated. In this way, in accordance with the generating period of the clock pulse (a), a relative moving speed is controlled.

System for processing common use information

Abstract: PURPOSE:To simplify a constitution by using a special frame in an information processing system where a clock master station, nodes and an information processor are connected in loop and the said information processor is used in common from the nodes. CONSTITUTION:The figure shows a frame format used for this information processing system. A start code 106 is transmitted periodically from the clock master clock. Communication information 100 is divided corresponding to the input/ output channel number of the information processor. Control information 104 is assigned fixedly to each node. A calling code is transmitted to one's own time slot location of the control information 104 in the calling from a node. The master station transmits the information number corresponding to an idle input/ output channel in the same time slot. The calling node communicates with the information processor by utilizing the information channel.

Driving circuit of solid-state image pickup device

Abstract: PURPOSE:To prevent malfunction of a driving circuit by waveform-shaping a pulse deciding the starting time of a pulse driving a horizontal transferring means by a pulse frequency-divided from a master clock CONSTITUTION:The master clock fM from an oscillating circuit 11 is received by a 1/2 frequency divider 12 and a 1/7 frequency divider 13, and a 2MHz pulse being an output of the divider 13 is inputted to a 1/130 frequency divider 14 and a phiHCLR clock circuit 30 The output of the circuit 14 is inputted to a vertical synchronizing pulse generating circuit 16 and a horizontal synchronizing pulse generating decoder 15 The circuit 16 generates a vertical synchronizing pulse group, and the circuit 15 generates a horizontal synchronizing pulse group and outputs a phiHCLR pulse, which is inputted to the circuit 30 The circuit 30 outputs the phiHCLRL pulse less in the phase change to the clock fM by waveform-shaping the phiHCLR pulse by the 2MHz pulse again and the phiHCLRL pulse is inputted to the circuit 12 Thus, the circuit 12 outputs a horizontal transfer pulse group phiH without producing a shift of pulse from the clock fM and the phiHCLRL pulse

Improvements in or relating to master clocks

Abstract: Slave devices such as slave clocks, loudspeakers, buzzers and the like are controlled by means of a master clock having a plurality of output ports (P0 to P27) through which control pulses are supplied to the slave devices. An identity register (209) is associated with each port and has entered therein the pulse type to be transmitted through that port. A waveform generator (203) supplies different clock pulses in normal and fast rate pairs (C1 to C6). Waveform selector means severally associated with the individual ports (P0 to P27) is supplied with pulses from the waveform generator (203) and is arranged to pass only the pair of pulse trains (C1, C2 or C3, C4 or C5, C6) entered in the identity register (209). A counter (215) is arranged to be incremented by normal rate pulses from the waveform selector (216, 219). A gate (218) receives fast rate pulses from the waveform selector (216) and is enabled when slave device power (PE) is available and the state of counter (215) is positive, the gate 218 then decrements the counter (215) as output pulses occur with the result that until the state of the counter (215) is zero the gate (218) transmits output pulses in sympathy with the fast rate pulse train and thereafter transmits output pulses in sympathy with the slow rate pulse train.

Magnetic inversion type display secondary clock

Abstract: PURPOSE:To correct quickly a time, to save an electric power, to extend a mechanical life and to detect automatically the end of the correction to reset to the normal display by erasing a display when correcting a display time, and operating only a counter by a correcting pulse. CONSTITUTION:At the normal time, a synchronizing signal (a) is inputted to a clock shaping part 2 from a master clock 1, and a signal (b) is inputted to a clock input of a counter 3. Subsequently, the first monostable multivibrator circuit 4 outputs a signal (c) of pulse width twA by synchronizing with an output of the clock shaping part 2. Accordingly, the output of the first monostable multivibrator circuit 4 is inputted to a display part 8 simultaneously with a 7- segment signal outputted from a decoder 6, and a time counting operation is executed at every one minute to display on the display part 8. Subsequently, the display time is corrected to turn on a reset switch 7, to input an ''H'' signal and to reset the counter 3. The output of the second monostable multivibrator circuit 11 falls to invert a flip-flop 10, to release the blanking of the decoder 6, to invert the output of the counter 3 to the 7-segment signal and output from the decoder 6, and a normal time is displayed on the display part 8.

Time correction apparatus

Abstract: PURPOSE:To make it possible to hold the transmission path between a master clock and a slave clock to a normal state even if a correction circuit gets out of order, by preventing a correction gate circuit from being inserted into a normal pulse transmission path. CONSTITUTION:A master clock 1 and a slave clock 2 are connected by a normal pulse transmission path 3 and, for example, one normal pulse is transmitted to the slave clock 2 at every 30sec through said normal pulse transmission path 3 as is conventional and the slave clock 2 is operated at every 30sec to allow display to step intermittently. When the display of the slave clock 2 is corrected to a delay direction, a reversible change-over switch 4 is changed over. When a corrected time is inputted to memory 7, a comparator 8 performs the comparing operation with the count value of a counter 10. When the comparator 8 detects non-coincidence, an H-logical signal is applied to one terminal of a gate 9. By this method, the gate 9 is controlled so as to be opened and the correction pulse outputted from a correction pulse generator 6 is outputted to be applied to the slave clock 2 through the gate 9.

Delay time measuring device of ic tester

Abstract: PURPOSE:To measure the large delay time of an IC tester by controlling a counter which counts a master clock when a mode waveform is inputted and when an output responding to the mode waveform is outputted. CONSTITUTION:The mode waveform is outputted from a pattern memory 1 by a pattern processor 2 and stored in a pattern output buffer 3. A pattern from this buffer 3 is inputted to an IC6 to be measured through a shaping circuit 4, etc., and inputted to a multiplexer 9 to which the master clock C is impressed, so that the counter 11 starts counting the clock C at the point of time when the mode waveform is inputted. The counter 11 is controlled through a multiplexer 10 impressed with a decision output from a comparing circuit 8 corresponding to the output of the IC6 and the expected value of the buffer 3 and this counting is carried on until the IC6 generates an output corresponding to the mode waveform. Then, the delay time of the IC tester which exceeds the capacity of a fail analyzing memory is measured by the counted value of the counter 11 with high precision.

Master and slave clock device

Abstract: PURPOSE:To increase a mean supply current sent out of a master clock and increase electric power supply to a slave clock by transmitting auxiliary pulses additionally during a stop period of clocking pulses transmitted from the master clock to the slave clock. CONSTITUTION:This master and slave clock device has the master clock 1 and slave clock 4 and transmits auxiliary pulses which has a pulse crest value or pulse width less than that of clocking pulses additionally during the stop period of clocking pulses sent out of the master clock 1. The slave clock 4, on the other hand, extracts the sent clocking pulses by a voltage comparator 6, and transfers them to a counter 7 and also applies the composite signal of the clocking pulses and auxiliary pulses to a rectifying and smoothing circuit 11. The rectifying and smoothing circuit 11 converts the composite signal into a DC voltage, which is supplied as a power source to respective circuits 7-9 constituting the slave clock.

Corrector for magnetic inversion type digital slave clock

Abstract: PURPOSE:To enable the correction of only the slave clock wrong in the display time by correcting a time display section with the operation of a reset start switch and a correction switch CONSTITUTION:A master clock 1 containing a normal signal formation section and a correction signal formation section 17 is provided with a correction switch 6 for starting the correction signal formation section 17 and a voltage conversion means 18 for differentiating the voltage level of a correction signal from the normal signal to send out both signals through a signal line 8 A secondary clock 7 in which an output of a counter 22 for counting both the signals is inputted into a time display section 9 to display time through a decoder 23 and a driver 24 is provided with a signal control circuit 21 which discriminates these signals at the initial stage of the counter 22 to output either signal and a reset start switch 10 adapted to reset the counter 22 while having the correction signal outputting from the control circuit 21 Then, the time display section 9 is corrected by the operation of the switches 10 and 6